arm-hyp haskell: rephrase VIRQ inject decode after kernel changes
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@ -123,13 +123,13 @@ IO pages are invoked using InvokePage (cap contains a bit indicating it is an IO
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FIXME ARMHYP move HyperReg definition (to Hardware?)
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> type HyperReg = Word32 -- FIXME ARMHYP can abstract
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> type HyperReg = Int -- FIXME ARMHYP can abstract
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> type HyperRegVal = Word32 -- FIXME ARMHYP can abstract
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> data VCPUInvocation
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> = VCPUSetTCB (PPtr VCPU) (PPtr TCB)
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> -- XXX ARMHYP vcpu index group priority virq
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> | VCPUInjectIRQ (PPtr VCPU) Word8 Word8 Word8 Word16
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> -- XXX ARMHYP vcpu index virq
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> | VCPUInjectIRQ (PPtr VCPU) Int VIRQ
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> | VCPUReadRegister (PPtr VCPU) HyperReg
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> | VCPUWriteRegister (PPtr VCPU) HyperReg HyperRegVal
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> deriving (Show, Eq)
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@ -165,13 +165,15 @@ but this structure is never manipulated as a whole.
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FIXME ARMHYP move to platform
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> type VIRQ = Word32
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> gicVCPUMaxNumLR = (64 :: Int)
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> data GICVCPUInterface = VGICInterface {
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> vgicHCR :: Word32,
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> vgicVMCR :: Word32,
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> vgicAPR :: Word32,
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> vgicLR :: Array Int Word32
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> vgicLR :: Array Int VIRQ
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> }
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> deriving Show
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@ -141,15 +141,27 @@ Currently, there is only one VCPU register available for reading/writing by the
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\subsection{VCPU: inject IRQ}
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FIXME ARMHYP: this does not at this instance correspond to exactly what the C
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does, but it is the value that is stored inside of lr in the vgic
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> makeVIRQ :: Word32 -> Word32 -> Word32 -> VIRQ
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> makeVIRQ group prio irq =
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> (group `shiftL` groupShift) .|. (prio `shiftL` prioShift) .|. irq .|.
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> irqPending .|. eoiirqen
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> where groupShift = 30
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> prioShift = 23
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> irqPending = bit 28
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> eoiirqen = bit 19
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> decodeVCPUInjectIRQ :: [Word] -> ArchCapability ->
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> KernelF SyscallError ArchInv.Invocation
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> decodeVCPUInjectIRQ (mr0:mr1:_) cap@(VCPUCap {}) =
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> do
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> let vcpuPtr = capVCPUPtr cap
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> let vid = (fromIntegral (mr0 .&. 0xffff) :: Word16)
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> let priority = fromIntegral $ (mr0 `shiftR` 16) .&. 0xff
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> let group = fromIntegral $ (mr0 `shiftR` 24) .&. 0xff
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> let index = ((fromIntegral $ mr1 .&. 0xff) :: Word8)
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> let vid = mr0 .&. 0xffff
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> let priority = (mr0 `shiftR` 16) .&. 0xff
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> let group = (mr0 `shiftR` 24) .&. 0xff
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> let index = mr1 .&. 0xff
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>
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> rangeCheck vid (0::Int) ((1 `shiftL` 10) - 1)
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> rangeCheck priority (0::Int) 31
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@ -157,11 +169,11 @@ Currently, there is only one VCPU register available for reading/writing by the
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> gic_vcpu_num_list_regs <- withoutFailure $
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> gets (armKSGICVCPUNumListRegs . ksArchState)
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> rangeCheck index 0 gic_vcpu_num_list_regs
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> vcpu <- withoutFailure $ getObject vcpuPtr
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> let x = addressTranslateS1CPR
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> let vcpuLR = vgicLR $ vcpuVGIC vcpu
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> when (vcpuLR ! (fromIntegral index) .&. vgicIRQMask == vgicIRQActive) $ throw DeleteFirst
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> return $ InvokeVCPU $ VCPUInjectIRQ vcpuPtr (fromIntegral index) group priority vid
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> vcpuLR <- withoutFailure $ liftM (vgicLR . vcpuVGIC) $ getObject vcpuPtr
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> when (vcpuLR ! (fromIntegral index) .&. vgicIRQMask == vgicIRQActive) $
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> throw DeleteFirst
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> let virq = makeVIRQ (fromIntegral group) (fromIntegral priority) (fromIntegral vid)
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> return $ InvokeVCPU $ VCPUInjectIRQ vcpuPtr (fromIntegral index) virq
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> decodeVCPUInjectIRQ _ _ = throw TruncatedMessage
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\subsection{VCPU: perform and decode main functions}
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@ -173,7 +185,7 @@ Currently, there is only one VCPU register available for reading/writing by the
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> invokeVCPUReadReg vcpuPtr reg
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> performARMVCPUInvocation (VCPUWriteRegister vcpuPtr reg val) =
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> invokeVCPUWriteReg vcpuPtr reg val
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> performARMVCPUInvocation (VCPUInjectIRQ vcpuPtr _ _ _ _) = error "FIXME ARMHYP TODO"
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> performARMVCPUInvocation (VCPUInjectIRQ vcpuPtr _ _) = error "FIXME ARMHYP TODO"
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> decodeARMVCPUInvocation :: Word -> [Word] -> CPtr -> PPtr CTE ->
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> ArchCapability -> [(Capability, PPtr CTE)] ->
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