aspec/haskell: clean out resolved FIXMEs
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@ -34,7 +34,7 @@ definition
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init_irq_node_ptr :: word32 where
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"init_irq_node_ptr = kernel_base + 0x8000"
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(* FIXME: It is easy to remove a memory slot here, but once if we want to reserve other slots of memory, we have to do the proof of disjoint for example state again.
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(* It is easy to remove a memory slot here, but once if we want to reserve other slots of memory, we have to do the proof of disjoint for example state again.
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Comment is left here so that next time we need 4k memory, we don't need to fix example state and can simply change its name. *)
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definition
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init_globals_frame :: word32 where
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@ -80,7 +80,7 @@ definition
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tcb_mcpriority = minBound,
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tcb_arch = init_arch_tcb
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\<rparr>,
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init_globals_frame \<mapsto> ArchObj (DataPage False ARMSmallPage), (* FIXME: same reason as why we kept the definition of init_globals_frame *)
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init_globals_frame \<mapsto> ArchObj (DataPage False ARMSmallPage), (* same reason as why we kept the definition of init_globals_frame *)
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init_global_pd \<mapsto> ArchObj (PageDirectory global_pd)
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)"
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@ -86,7 +86,6 @@ datatype page_invocation
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datatype vcpu_invocation =
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VCPUSetTCB obj_ref (*vcpu*) obj_ref (*tcb*)
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(*FIXME ARMHYP: canonise canonical types for VCPUInjectIRQ *)
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| VCPUInjectIRQ obj_ref nat virq
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| VCPUReadRegister obj_ref vcpureg
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| VCPUWriteRegister obj_ref vcpureg machine_word
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@ -159,9 +159,8 @@ definition
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datatype arch_fault =
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VMFault vspace_ref "machine_word list"
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(* FIXME ARMHYP are these truly arch-independant, or just in the current C version *)
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| VGICMaintenance "data option" (* idx *) (* idxValid? second arguments? *)
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| VCPUFault data (* hsr *) (* FIXME ARMHYP: this is a 64-bit struct, 2x data? *)
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| VGICMaintenance "data option" (* idx *)
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| VCPUFault data (* hsr *)
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end
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@ -39,7 +39,7 @@ subsection "VCPU: Set TCB"
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definition decode_vcpu_set_tcb :: "arch_cap \<Rightarrow> (cap \<times> cslot_ptr) list \<Rightarrow> (arch_invocation,'z::state_ext) se_monad"
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where "decode_vcpu_set_tcb cap extras \<equiv> case (cap, extras) of
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(VCPUCap v, fs#_) \<Rightarrow> (case fs of
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(ThreadCap t, _) \<Rightarrow> returnOk $ InvokeVCPU $ VCPUSetTCB v t (* FIXME ARMHYP C code calls deriveCap here before checking the cap type, discuss with kernel team *)
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(ThreadCap t, _) \<Rightarrow> returnOk $ InvokeVCPU $ VCPUSetTCB v t
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| _ \<Rightarrow> throwError IllegalOperation)
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|(VCPUCap v, _) \<Rightarrow> throwError TruncatedMessage
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| _ \<Rightarrow> throwError IllegalOperation"
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@ -116,7 +116,8 @@ where
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text {* VCPU : inject IRQ *}
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(* ARMHYP FIXME see comment in VCPU_H *)
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(* This following function does not correspond to exactly what the C does, but
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it is the value that is stored inside of lr in the vgic *)
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definition make_virq :: "obj_ref \<Rightarrow> obj_ref \<Rightarrow> obj_ref \<Rightarrow> virq" where
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"make_virq grp prio irq \<equiv>
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let
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@ -102,8 +102,7 @@ where
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text {* Cancel all message operations on threads queued in a notification
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endpoint. *}
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text {* Miscellaneous NTFN binding stuff
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FIXME! *}
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(* FIXME: Miscellaneous NTFN binding stuff, move upwards? *)
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abbreviation
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ntfn_set_bound_tcb :: "notification \<Rightarrow> obj_ref option \<Rightarrow> notification"
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where
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@ -341,7 +340,6 @@ where
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text {* Cancel the message receive operation of a thread queued in an
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notification object. *}
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(* FIXME: need some way of easily retrieving ntfnBoundTCB? *)
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definition
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cancel_signal :: "obj_ref \<Rightarrow> obj_ref \<Rightarrow> (unit,'z::state_ext) s_monad"
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where
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@ -134,8 +134,8 @@ definition
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(* FIXME: we need a sensible place for these configurable constants. *)
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definition
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reset_chunk_bits :: nat
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where "reset_chunk_bits = 8"
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reset_chunk_bits :: nat where
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"reset_chunk_bits = 8"
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definition
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get_free_ref :: "obj_ref \<Rightarrow> nat \<Rightarrow> obj_ref" where
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@ -66,11 +66,10 @@ where
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| "arch_same_region_as (PML4Cap r _) c' = (\<exists>r' d'. c' = PML4Cap r' d' \<and> r = r')"
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| "arch_same_region_as ASIDControlCap c' = (c' = ASIDControlCap)"
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| "arch_same_region_as (ASIDPoolCap r _) c' = (\<exists>r' d'. c' = ASIDPoolCap r' d' \<and> r = r')"
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(* FIXME x64-vtd: *)
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(*
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(* FIXME x64-vtd:
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| "arch_same_region_as (IOPageTableCap r _ _) c = (is_IOPageTableCap c \<and> aobj_ref c = Some r)"
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| "arch_same_region_as (IOSpaceCap d_id pci_d) c = (is_IOSpaceCap c \<and> cap_io_pci_device c = pci_d)"
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--"FIXME: should this also check domain id equality? C kernel does not"
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FIXME x64-vtd: should this also check domain id equality? C kernel does not"
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*)
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| "arch_same_region_as (IOPortCap frst lst) c' =
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(\<exists>frst' lst'. c' = IOPortCap frst' lst' \<and> frst' = frst \<and> lst' = lst)"
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@ -87,7 +86,6 @@ definition
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| (IOPortControlCap, IOPortCap f' l') \<Rightarrow> False
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| _ \<Rightarrow> arch_same_region_as cp cp')"
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(* Proofs don't want to see this definition *)
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declare same_aobject_as_def[simp]
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definition
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@ -81,7 +81,7 @@ datatype page_invocation
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(page_iomap_cap: cap)
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(page_iomap_ct_clot: cslot_ptr)
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(page_iomap_asid: iopte)
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(page_iomap_entries: "obj_ref") (*FIXME: double check plz*)*)
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(page_iomap_entries: "obj_ref") *)
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| PageGetAddr
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(page_get_paddr: obj_ref)
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@ -38,14 +38,13 @@ definition
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where
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"sanitise_and_flags \<equiv> mask 12 && ~~ bit 8 && ~~ bit 3 && ~~ bit 5"
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(* FIXME x64: this is disgusting *)
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definition
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sanitise_register :: "bool \<Rightarrow> register \<Rightarrow> machine_word \<Rightarrow> machine_word"
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where
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"sanitise_register t r v \<equiv>
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let val = (if (r = FaultIP \<or> r = NextIP) then
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if (v > 0x00007fffffffffff \<and> v < 0xffff800000000000) then 0 else v
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else v)
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let val = (if r = FaultIP \<or> r = NextIP
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then if v > 0x00007fffffffffff \<and> v < 0xffff800000000000 then 0 else v
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else v)
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in
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if r = FLAGS then (val || sanitise_or_flags) && sanitise_and_flags else val"
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@ -338,11 +338,6 @@ check_mapping_pptr :: "machine_word \<Rightarrow> vm_page_entry \<Rightarrow> bo
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| VMPDPTE (HugePagePDPTE base _ _) \<Rightarrow> base = addrFromPPtr pptr
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| _ \<Rightarrow> False"
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(* FIXME: move to generic *)
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text {* Raise an exception if a property does not hold. *}
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definition
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throw_on_false :: "'e \<Rightarrow> (bool,'z::state_ext) s_monad \<Rightarrow> ('e + unit,'z::state_ext) s_monad" where
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"throw_on_false ex f \<equiv> doE v \<leftarrow> liftE f; unlessE v $ throwError ex odE"
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text {* Unmap a mapped page if the given mapping details are still current. *}
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definition
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@ -47,15 +47,6 @@ definition
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od)
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)"
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(*FIXME x64: Current C code doesn't work for addresses above 32 bits.
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This is meant to take a base address and craft a default
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gdt_data structure. *)
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definition
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base_to_gdt_data_word :: "machine_word \<Rightarrow> machine_word" where
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"base_to_gdt_data_word = undefined"
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text {* Switch to a thread's virtual address space context and write its IPC
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buffer pointer into the globals frame. Clear the load-exclusive monitor. *}
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@ -66,7 +57,6 @@ definition
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arch_switch_to_thread :: "obj_ref \<Rightarrow> (unit,'z::state_ext) s_monad" where
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"arch_switch_to_thread t \<equiv> set_vm_root t"
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(* x64 done *)
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definition
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arch_switch_to_idle_thread :: "(unit,'z::state_ext) s_monad" where
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"arch_switch_to_idle_thread \<equiv> do
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@ -74,7 +64,6 @@ definition
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set_vm_root thread
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od"
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(* x64 done *)
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definition
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arch_activate_idle_thread :: "obj_ref \<Rightarrow> (unit,'z::state_ext) s_monad" where
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"arch_activate_idle_thread t \<equiv> return ()"
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@ -182,7 +171,7 @@ perform_page_invocation :: "page_invocation \<Rightarrow> (unit,'z::state_ext) s
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| _ \<Rightarrow> fail
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| None \<Rightarrow> return ()
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| _ \<Rightarrow> fail)
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(* | PageIOMap asid cap ct_slot entries \<Rightarrow> undefined (* FIXME unimplemented *)*)
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(* | PageIOMap asid cap ct_slot entries \<Rightarrow> undefined *)
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| PageGetAddr ptr \<Rightarrow> do
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paddr \<leftarrow> return $ fromPAddr $ addrFromPPtr ptr;
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ct \<leftarrow> gets cur_thread;
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@ -191,8 +180,7 @@ perform_page_invocation :: "page_invocation \<Rightarrow> (unit,'z::state_ext) s
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set_message_info ct msg_info
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od)"
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text {* PageTable capabilities confer the authority to map and unmap page
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tables. *}
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text {* PageTable capabilities confer the authority to map and unmap page tables. *}
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definition
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perform_page_table_invocation :: "page_table_invocation \<Rightarrow> (unit,'z::state_ext) s_monad" where
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"perform_page_table_invocation iv \<equiv>
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@ -67,7 +67,6 @@ section {* Architecture-specific objects *}
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datatype table_attr = Accessed | CacheDisabled | WriteThrough | ExecuteDisable
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type_synonym table_attrs = "table_attr set"
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(* FIXME: better keep two separate sets? *)
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datatype frame_attr = PTAttr table_attr | Global | PAT | Dirty
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type_synonym frame_attrs = "frame_attr set"
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@ -207,8 +207,8 @@ Currently, there is only one VCPU register available for reading/writing by the
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\subsection{VCPU: inject IRQ}
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FIXME ARMHYP: this does not at this instance correspond to exactly what the C
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does, but it is the value that is stored inside of lr in the vgic
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This following function does not correspond to exactly what the C does, but
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it is the value that is stored inside of lr in the vgic
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> makeVIRQ :: Word -> Word -> Word -> VIRQ
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> makeVIRQ grp prio irq =
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