risc-v simpl-export: ignore `arch_init_freemem`
A new version of `arch_init_freemem` for RISC-V introduces some heap access patterns which are not well supported by SimplExportAndRefine. `arch_init_freemem` is already ignored by `graph-refine`, because it is inlined into `init_freemem`, which contains complex loops. Therefore, we don't lose anything by ignoring it in SimplExportAndRefine. Although the problem only manifests on RISC-V, we ignore it on all platforms. Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
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@ -65,7 +65,7 @@ lemma snd_snd_gs_new_frames_new_cnodes[simp]:
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ML \<open>
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ML \<open>
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\<comment>\<open> VER-1166 \<close>
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\<comment>\<open> VER-1166 \<close>
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val blacklist = ["Kernel_C.reserve_region", "Kernel_C.merge_regions"]
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val blacklist = ["Kernel_C.reserve_region", "Kernel_C.merge_regions", "Kernel_C.arch_init_freemem"]
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val dbg = ProveSimplToGraphGoals.new_debug blacklist [];
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val dbg = ProveSimplToGraphGoals.new_debug blacklist [];
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\<close>
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\<close>
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