aarch64 haskell: use ppn concept for PageTablePTEs

Don't store the bottom 12 bits of the base address for page table PTEs,
because we know they are zero. This gives us implicit alignment to
pageBits in the page table walker.

The C code stores only 36 significant bits, whereas this commit still
uses a full 64-bit machine word for the ppn in Haskell. To be adjusted
in a future change.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>

spec/haskell/src/SEL4/Kernel/VSpace/AARCH64.hs

@@ -128,7 +128,8 @@ isPagePTE (PagePTE {}) = True
 isPagePTE _ = False
 
 getPPtrFromPTE :: PTE -> PPtr PTE
-getPPtrFromPTE pte = ptrFromPAddr $ pteBaseAddress pte
+getPPtrFromPTE pte =
+    ptrFromPAddr (if isPagePTE pte then pteBaseAddress pte else ptePPN pte `shiftL` pageBits)
 
 -- how many bits there are left to be translated at a given level (0 = bottom
 -- level). This counts the bits being translated by the levels below the current one, so
@@ -614,7 +615,7 @@ decodeARMPageTableInvocationMap cte cap vptr attr vspaceCap = do
     oldPTE <- withoutFailure $ getObject slot
     when (bitsLeft == pageBits || oldPTE /= InvalidPTE) $ throw DeleteFirst
     let pte = PageTablePTE {
-            pteBaseAddress = addrFromPPtr (capPTBasePtr cap) }
+            ptePPN = addrFromPPtr (capPTBasePtr cap) `shiftR` pageBits }
     let vptr = vptr .&. complement (mask bitsLeft)
     return $ InvokePageTable $ PageTableMap {
         ptMapCap = ArchObjectCap $ cap { capPTMappedAddress = Just (asid, vptr) },

spec/haskell/src/SEL4/Machine/Hardware/AARCH64.hs

@@ -336,7 +336,7 @@ data PTE
         pteDevice :: Bool,
         pteRights :: VMRights }
     | PageTablePTE {
-        pteBaseAddress :: PAddr }
+        ptePPN :: PAddr }
     deriving (Show, Eq)
 
 {- Simulator callbacks -}