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riscv haskell: sync register set definition with C 

Now in sync with seL4 master@63ed19c9b7d972eb4af73c666484e277b0d4cf83
This commit is contained in:
Gerwin Klein 2019-03-14 18:00:33 +11:00 committed by Rafal Kolanski
parent f2a6566192
commit b7bf3a9e22
1 changed files with 2 additions and 2 deletions
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4
spec/haskell/src/SEL4/Machine/RegisterSet/RISCV64.hs
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@ -43,10 +43,10 @@ badgeRegister :: Register
badgeRegister = A0
frameRegisters :: [Register]
frameRegisters = FaultIP : [LR .. A6]
frameRegisters = FaultIP : [LR .. T5]
gpRegisters :: [Register]
gpRegisters = []
gpRegisters = [T6]
exceptionMessage :: [Register]
exceptionMessage = [FaultIP, SP, A7]