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arm-hyp execspec: add irqVGICMaintenane and initInterruptController 

with caseconvs, generated files
This commit is contained in:
Miki Tanaka 2016-07-27 21:51:07 +10:00 committed by Alejandro Gomez-Londono
parent 629ea900b7
commit c32e6552e5
7 changed files with 91 additions and 4 deletions
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2
spec/design/m-skel/ARM_HYP/MachineTypes.thy
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@ -8,7 +8,7 @@
* @TAG(GD_GPL)
*)
chapter "ARM_HYP Machine Types"
chapter {* ARM\_HYP Machine Types *}
theory MachineTypes
imports

2
spec/design/skel/ARM_HYP/ArchHypervisor_H.thy
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@ -26,6 +26,8 @@ context Arch begin global_naming ARM_HYP_H
defs handleHypervisorFault_def:
"handleHypervisorFault arg1 hyp \<equiv> case hyp of ARMNoHypFaults \<Rightarrow> haskell_fail []"
#INCLUDE_HASKELL SEL4/Object/VCPU/ARM_HYP.lhs CONTEXT ARM_HYP_H ArchInv=Arch ONLY vcpuDisable vcpuEnable vcpuRestore vcpuSave vcpuSwitch vcpuInvalidateActive vcpuCleanInvalidateActive
end
end

8
spec/design/skel/ARM_HYP/ArchInterrupt_H.thy
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@ -13,7 +13,13 @@ imports "../RetypeDecls_H" "../CNode_H" "../InterruptDecls_H" ArchInterruptDecls
begin
context Arch begin global_naming ARM_HYP_H
#INCLUDE_HASKELL SEL4/Object/Interrupt/ARM_HYP.lhs Arch= CONTEXT ARM_HYP_H bodies_only ArchInv=ArchRetypeDecls_H
#INCLUDE_HASKELL SEL4/Object/Interrupt/ARM_HYP.lhs Arch= CONTEXT ARM_HYP_H bodies_only ArchInv=ArchRetypeDecls_H NOT initInterruptController
definition initInterruptController :: "unit kernel"
where "initInterruptController \<equiv> (do
setIRQState IRQReserved $ irqVGICMaintenance;
return ()
od)"
end
end

1
spec/design/skel/ARM_HYP/ArchVSpace_H.thy
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@ -17,6 +17,7 @@ imports
"../CNode_H"
"../KI_Decls_H"
ArchVSpaceDecls_H
ArchHypervisor_H
begin
context Arch begin global_naming ARM_HYP_H

3
spec/design/skel/ARM_HYP/VCPU_H.thy
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@ -18,7 +18,8 @@ begin
context Arch begin global_naming ARM_HYP_H
#INCLUDE_HASKELL_PREPARSE SEL4/Object/Structures.lhs CONTEXT ARM_HYP_H
#INCLUDE_HASKELL SEL4/Object/VCPU/ARM_HYP.lhs CONTEXT ARM_HYP_H ArchInv=Arch
#INCLUDE_HASKELL SEL4/Object/VCPU/ARM_HYP.lhs CONTEXT ARM_HYP_H ArchInv=Arch NOT vcpuDisable vcpuEnable vcpuRestore vcpuSave vcpuSwitch vcpuInvalidateActive vcpuCleanInvalidateActive
end
end

3
spec/machine/ARM_HYP/Platform.thy
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@ -78,6 +78,9 @@ definition
maxIRQ :: "irq" where
"maxIRQ \<equiv> 0x9F"
definition irqVGICMaintenance :: "irq"
where "irqVGICMaintenance \<equiv> 25"
end
end

76
tools/haskell-translator/caseconvs
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@ -1760,7 +1760,7 @@ case \x of ((mr0:mr1:_), cap@(VCPUCap {})) -> (_, _) -> ---> let (ls, cap) = \x
else ->2
case \x of cap@(PageDirectoryCap {}) -> cap@(PageTableCap {}) -> cap@(PageCap {}) -> ASIDControlCap -> cap@(ASIDPoolCap {}) -> (VCPUCap {}) -> ---> let cap = \x in
case \x of cap@(PageDirectoryCap {}) -> cap@(PageTableCap {}) -> cap@(PageCap {}) -> ASIDControlCap -> cap@(ASIDPoolCap {}) -> (VCPUCap {}) -> ---> let cap = \x in
if isPageDirectoryCap cap
then ->1
else if isPageTableCap cap
@ -1775,3 +1775,77 @@ case \x of cap@(PageDirectoryCap {}) -> cap@(PageTableCap {}) -> cap@(PageCap {}
then ->6
else undefined
case \x of ((ASIDPoolCap { capASIDBase = b, capASIDPool = ptr }), True) -> ((PageDirectoryCap { capPDMappedASID = Just a, capPDBasePtr = ptr }), True) -> ((PageTableCap { capPTMappedAddress = Just (a, v), capPTBasePtr = ptr }), True) -> ((cap@PageCap { capVPMappedAddress = Just (a, v), capVPSize = s, capVPBasePtr = ptr }), _) -> ((VCPUCap { capVCPUPtr = vcpu }), True) -> (_, _) -> ---> let (cap, bl) = \x in
if isASIDPoolCap cap \<and> bl
then let b = capASIDBase cap; ptr = capASIDPool cap
in ->1
else if isPageDirectoryCap cap \<and> bl \<and> capPDMappedASID cap \<noteq> None
then let a = the (capPDMappedASID cap); ptr = capPDBasePtr cap
in ->2
else if isPageTableCap cap \<and> bl \<and> capPTMappedAddress cap \<noteq> None
then let (a, v) = the (capPTMappedAddress cap); ptr = capPTBasePtr cap
in ->3
else if isPageCap cap \<and> capVPMappedAddress cap \<noteq> None
then let (a, v) = the (capVPMappedAddress cap); s = capVPSize cap; ptr = capVPBasePtr cap
in ->4
else if isVCPUCap cap \<and> bl
then let vcpu = capVCPUPtr cap
in ->5
else ->6
case \x of (cap@PageCap {}) -> (cap@PageTableCap { capPTBasePtr = ptr }) -> (cap@PageDirectoryCap { capPDBasePtr = ptr }) -> ASIDControlCap -> (cap@ASIDPoolCap { capASIDBase = base, capASIDPool = ptr }) -> (cap@VCPUCap { capVCPUPtr = vcpu }) -> ---> let cap = \x in
if isPageCap cap
then ->1
else if isPageTableCap cap
then let ptr = capPTBasePtr cap
in ->2
else if isPageDirectoryCap cap
then let ptr = capPDBasePtr cap
in ->3
else if isASIDControlCap cap
then ->4
else if isASIDPoolCap cap
then let base = capASIDBase cap; ptr = capASIDPool cap
in ->5
else if isVCPUCap cap
then let vcpu = capVCPUPtr cap
in ->6
else undefined
case \x of ((ASIDPoolCap { capASIDBase = b, capASIDPool = ptr }), True) -> ((PageDirectoryCap { capPDMappedASID = Just a, capPDBasePtr = ptr }), True) -> ((PageTableCap { capPTMappedAddress = Just (a, v), capPTBasePtr = ptr }), True) -> ((cap@PageCap { capVPMappedAddress = Just (a, v), capVPSize = s, capVPBasePtr = ptr }), _) -> ((VCPUCap { capVCPUPtr = vcpu }), True) -> (_, _) -> ---> let (cap, bl) = \x in
if isASIDPoolCap cap \<and> bl
then let b = capASIDBase cap; ptr = capASIDPool cap
in ->1
else if isPageDirectoryCap cap \<and> bl \<and> capPDMappedASID cap \<noteq> None
then let a = the (capPDMappedASID cap); ptr = capPDBasePtr cap
in ->2
else if isPageTableCap cap \<and> bl \<and> capPTMappedAddress cap \<noteq> None
then let (a, v) = the (capPTMappedAddress cap); ptr = capPTBasePtr cap
in ->3
else if isPageCap cap \<and> capVPMappedAddress cap \<noteq> None
then let (a, v) = the (capVPMappedAddress cap); s = capVPSize cap; ptr = capVPBasePtr cap
in ->4
else if isVCPUCap cap \<and> bl
then let vcpu = capVCPUPtr cap
in ->5
else ->6
case \x of cap@(PageDirectoryCap {}) -> cap@(PageTableCap {}) -> cap@(PageCap {}) -> ASIDControlCap -> cap@(ASIDPoolCap {}) -> (VCPUCap {}) -> ---> let cap = \x in
if isPageDirectoryCap cap
then ->1
else if isPageTableCap cap
then ->2
else if isPageCap cap
then ->3
else if isASIDControlCap cap
then ->4
else if isASIDPoolCap cap
then ->5
else if isVCPUCap cap
then ->6
else undefined