Commit Graph

396 Commits

Author SHA1 Message Date
Gerwin Klein 33e6400f8a aspec: include doc build in ASpec again
Isabelle2020 doesn't allow sharing session directories between the document
session and non-document session. Instead of duplicating things, this commit
pulls the document build back into the ASpec session, but changes the build
such that the git revision is read directly from LaTeX, removing the
superfluous re-build for every git revision change (even when no relevant spec
file changed).

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein e7fb36b7e2 ROOT files: file reorg for new ROOT requirements
Isabelle2020 requires each session to declare it own set of directories that
may not overlap with other session's directories. This commit reorganises
files to comply with that requirement.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Miki Tanaka caf09bd3db aspec+ainvs: remove interrupt/irq from p_monad
- preemption in C is not associated to an irq
- updating aspec to reflect this so that we can have irq-independent
  preemptions (needed in MCS)

- proof fix for the above: remove intr

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2020-10-25 13:15:00 +11:00
Matthew Brecknell b77f83c57b riscv: rename sbadaddr -> stval
Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2020-08-26 15:24:06 +10:00
Gerwin Klein 6fd03279df riscv aspec: spec is in sync with C, the returned error is correct
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 9de5bb27e4 aspec: factor out arch_mask_irq_signal
On RISC-V we do not call mask_irq.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Victor Phan 461a798412 aspec: arch split on invokeIRQHandler
The RISCV implementation of invokeIRQHandler calls plic_complete_claim
instead of maskInterrupt. plicCompleteClaim is added as a machine op
and invokeIRQHandler has been arch split for the ACKIrq case.

Signed-off-by: Victor Phan <Victor.Phan@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 9bd06da4d7 riscv aspec+haskell: make mapped PTE invalid for insufficient rights
The RISC-V ISA spec does not allow PagePTEs with 000 for rwx rights,
because 000 is used to identify PageTablePTEs. Instead we write
InvalidPTEs, which has the same effect for the user.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein 1dccd9ceaf riscv aspec: update arch API type decoding to new order
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Rafal Kolanski cc367d61b2 riscv aspec+ainvs: update tcb bits to 10
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Rafal Kolanski c4f6572aff arm+arm-hyp: move TPIDRURO from vcpu to tcb context
Update specs and proofs for ARM platforms to contain TPIDRURO in the
TCB user context rather than treating it as a VCPU register, following
change in C.

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-05-15 13:14:24 +10:00
Gerwin Klein c68915b92b license: provide documentation under CC-BY-SA-4.0
Datat61 provides all docs under CC-BY-SA-4.0.
2020-03-16 14:19:15 +08:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Gerwin Klein 8d12d8e4be licenses: tag .md and document file 2020-03-02 18:52:15 +08:00
Rafal Kolanski f9ea44ef89 arm-hyp: update spec+proofs for multi-VM support
Highlights:
- new reserved IRQ and associated handler: VPPIEvent
- VPPI events are virtual interrupts we can forward to VMs; currently there is
  only one event: virtual timer interrupt
- VGICMaintenance and VPPIEvent can both receive late interrupts from hardware,
  which are now discarded instead of being delivered to current thread
- given only one possible VPPI event, simplifier tends to mop up more than it
  should, making some proofs fragile w.r.t. adding a new VPPI event
- the order of some lemmas/specs needed shuffling, as now VCPU code needs some
  interrupt code, which uses VCPU code
2020-02-19 10:52:07 +11:00
Zoltan Kocsis 788b4bd180 refactored irq_t structure (VER-1159) 2020-02-05 17:58:45 +11:00
Gerwin Klein f50985b448 abstract: use new invocation label enum 2020-02-03 12:56:19 +08:00
Victor Phan ff6c0d8a0a Move vcpu_switch into Arch_switchToThread and update proofs
Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.
2020-01-20 16:53:32 +11:00
Gerwin Klein 55aeefdb64 x64: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Gerwin Klein b820b13d06 riscv: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Victor Phan 1db6ae7cf0 riscv: add kdev_base/kdevBase to handle RISCVVSpaceDeviceWindow and update proofs
- Add HiFive.hs to replace Spike.hs, it's the same except for kdevBase
  addition.
- Originally called KDEV_PPTR in the C Code, to be changed to KDEV_BASE
  across all architectures.
- Add RISCVVSpaceDeviceWindow case for valid_uses_2 definition.
2019-11-13 16:27:30 +11:00
Victor Phan c7fb4dcf2b riscv aspec/ainvs: redefine kernel_elf_base to point to be kernelELFBase 2019-11-13 16:08:52 +11:00
Victor Phan 6f94fff163 riscv aspec/ainvs: rename kernel_base to kernel_elf_base 2019-11-13 16:08:42 +11:00
Victor Phan 55408a48af riscv aspec: implement IRQ check, decode and invoke control functions
These functions were originally doing throwError IllegalOperation or
returnOk (). Now they have been reimplemented to match the CSpec.

In arch_check_irq, an error is thrown if IRQ is greater than maxIRQ or
is equal to irqInvalid. The error that gets returned to the user however
is a RangeError from 1 to maxIRQ.
2019-11-12 18:28:40 +11:00
Victor Phan 79da089c2e riscv aspec: update for moving IPC buffer register to thread-local storage 2019-11-12 18:28:40 +11:00
Gerwin Klein a5e27933a5 riscv: cleanup; resolve remaining FIXMEs 2019-11-12 18:28:40 +11:00
Gerwin Klein 090894c990 riscv aspec+ainvs: define a consistent initial page table
Simpler than the real kernel layout, but will show that invariants are
consistent.
2019-11-12 18:28:39 +11:00
Gerwin Klein 9d81f85c38 riscv: force vptr alignment in PTMap decode
Instead of checking for alignment, mask out the bottom bits to force the
vptr stored in the cap into the correct alignment for the level to be mapped.

See also SELFOUR-2162
2019-11-12 18:28:39 +11:00
Gerwin Klein b5c47d552e riscv aspec+ainvs: perform_pg_inv_unmap: update cap in memory
The argument cap is the same as the one in memory, but it's less work to not
prove that.
2019-11-12 18:28:39 +11:00
Gerwin Klein 750746296f riscv aspec: unmap_page may be called with unmapped ASID
This means we can't use gets_the, which asserts, but need find_vspace_for_asid,
which can throw.
2019-11-12 18:28:39 +11:00
Gerwin Klein d4f3d7122c riscv aspec: fix addr conversions in set_vm_root
global_pt needs addrFromKPPtr, because it is an address that lives in the
kernel image, other pt's need addrFromPPtr because they are standard
kernel-virtual addresses.
2019-11-12 18:28:39 +11:00
Gerwin Klein c77b2126e0 riscv aspec: initialise SSTATUS register correctly 2019-11-12 18:28:39 +11:00
Gerwin Klein 5a7c2ef850 riscv aspec: correct comment for kernel_base; adjust idle_thread_ptr 2019-11-12 18:28:39 +11:00
Gerwin Klein 960636f744 riscv aspec: pick aligned addresses for pptr_base in initial example state. 2019-11-12 18:28:39 +11:00
Gerwin Klein 6dd45e2d5f riscv aspec: sync max_untyped_size with Haskell/C 2019-11-12 18:28:39 +11:00
Gerwin Klein 8e39bbbda9 riscv aspec: provide a constant for ppn word width 2019-11-12 18:28:38 +11:00
Gerwin Klein 430a345aeb riscv aspec: avoid type variable warning and freeindex increase 2019-11-12 18:28:38 +11:00
Victor Phan 0ae9614d30 riscv aspec: update PageMap to replace PageRemap (SELFOUR-161) 2019-10-10 11:26:41 +11:00
Victor Phan 2f04dc3694 x64 aspec: update PageMap to replace PageRemap (SELFOUR-161) 2019-10-10 11:26:33 +11:00
Victor Phan 12a7c2d441 arm-hyp aspec: update PageMap to replace PageRemap (SELFOUR-161) 2019-10-10 11:26:33 +11:00
Victor Phan c64e054c3f arm aspec: update PageMap to replace PageRemap (SELFOUR-161) 2019-10-10 11:26:33 +11:00
Victor Phan 90c0bd618f aspec doc: update for PageMap replacing Remap (SELFOUR-161) 2019-10-10 11:26:33 +11:00
MiladKetabi d934d25269 proof update for SELFOUR-1187: seL4 setPriority should attempt a direct schedule
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.
2019-10-06 18:31:19 +11:00
Gerwin Klein a1dca67543 riscv aspec/ainvs: resolve FIXMEs, reduce warnings
Mostly moved lemmas and definitions to more suitable locations.
Removed unused lemmas and commented-out code.
Resolved simple Isabelle warnings.
2019-07-31 16:56:26 +10:00
Gerwin Klein f8dc660baf riscv aspec/ainvs: move init_vspace_uses and canonical_user to spec
Needed to define an initial state that satisfies invariants.
2019-07-31 16:55:32 +10:00
Gerwin Klein 519b672d08 riscv aspec bugfix: need to check vaddr alignment for PT-map 2019-07-31 16:55:32 +10:00
Gerwin Klein 0feb5c1a1e riscv aspec: add check for top-level PT in PT unmap decode
See also SELFOUR-2158
2019-07-31 16:55:32 +10:00
Gerwin Klein af6e0765c5 riscv aspec+ainvs: spec bugfix for arch_finalise_cap; finish ArchFinalise 2019-07-31 16:55:32 +10:00
Gerwin Klein 82df777dd7 riscv aspec: fix spec bug in pt_lookup_from_level
This spec bug was inspired by slightly differently but similarly wrong C code
(SELFOUR-2091). Current change brings it into sync with the (correct, we think)
C. Proof update included.
2019-07-31 16:55:32 +10:00
Gerwin Klein 116009c1d7 riscv aspec: constrain asid type to asid_len
We previously had asids at machine word representation, but it turns out that
constraining them to actual asid_len is almost no overhead and saves us proving
invariants about asid sizes.
2019-07-31 16:55:32 +10:00