Commit Graph

71 Commits

Author SHA1 Message Date
Gerwin Klein a45adef66a all: remove theory import path references
In Isabelle2020, when isabelle jedit is started without a session
context, e.g. `isabelle jedit -l ASpec`, theory imports with path
references cause the isabelle process to hang.

Since sessions now declare directories, Isabelle can find those files
without path reference and we therefore remove all such path references
from import statements. With this, `jedit` and `build` should work with
and without explicit session context as before.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-11-02 10:16:17 +10:00
Gerwin Klein 7d24031854 arm ainvs: Isabelle2020 update
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein bce372b4fb ainvs: proof updates for new arch split functions
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Victor Phan a33df75acb riscv ainvs: update for invokeIRQHandler arch split spec change
Add appropriate lemmas for machine op plic_complete_claim.

Signed-off-by: Victor Phan <Victor.Phan@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Corey Lewis 9846cd42bb proof: update for crunch changes 2019-10-14 17:23:41 +11:00
Corey Lewis dd48e0d899 proof: update for wp changes
Updated 'wp_once' to 'wp (once)' and removed several stray uses of 'wp_trace'.
2019-10-14 17:12:18 +11:00
MiladKetabi d934d25269 proof update for SELFOUR-1187: seL4 setPriority should attempt a direct schedule
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.
2019-10-06 18:31:19 +11:00
Amirreza Zarrabi ac886401d7 ainvs: add support to thread id registers 2019-06-28 11:34:13 +10:00
Michael McInerney 4463e9750e SELFOUR-1198: update proofs for correct restart PC
Fixes a case where a thread can go from Running->Inactive->Restart and
use a restart PC that is out of date. An out of date restart PC occurs
when a thread was transitioned to running after being in a blocked
state, but was never scheduled and so did not execute the traps code
that updates the restart PC.

This also renames relevant register names for consistency across
architectures (FaultIP and NextIP).
2019-06-13 11:43:50 +10:00
Victor Phan c9094ccbb3 ainvs: update for new definition of set_object
Added set_object_wp_strong, which infers from a given hoare triple with
command set_object that the object of same type already exists in the
heap, and hoare_set_object_weaken_pre which does the same thing, but can
be applied on top of existing lemmas about set_object.

ainvs: improve proof of set_thread_state_runnable_valid_blocked

ainvs: change return value to a more general one

in_set_object has a return value that is empty '()', but the theorem
still holds true when replaced with a generic parameter 'rv' making it
easier to use this lemma.

ainvs: trivial - updated style of proof

ainvs: strengthen set_object_idle lemma

Add conditions imposed by valid_idle into precondition.
Thank you to Matt Brecknell for the help.

ainvs: abbreviated Hoare triples and proof fix

ainvs: restated set_object_wp_strong with auxiliary lemmas

ainvs: update for new definition of set_object

ainvs: update for new definition of set_object

Move in a few set_object and set_aobject theorems from x64 theory files
as these theorems were architecture generic.

ainvs: update for new definition of set_object

ainvs: update for new definition of set_object
2019-04-18 14:32:08 +10:00
Thibaut Perami d3548a5720 arm ainvs: Cleanup 2018-12-10 20:01:37 +11:00
Thibaut Perami 3f26cde16a arm ainvs: Update for GrantReply (SELFOUR-6) 2018-12-10 20:01:37 +11:00
Gerwin Klein 15bfcdd98b reduce DRefine dependencies from Refine to AInvs
This needs (and includes) some deduplication and moving of lemmas formerly in
refine.
2018-10-22 13:21:11 +11:00
Gerwin Klein 6b9d9d24dd Isabelle2018: new "op x" syntax; now is "(x)"
(result of "isabelle update_op -m <dir>")
2018-08-20 09:06:35 +10:00
Thomas Sewell 26049db669 Repair proofs for wpsimp/crunch changes.
A handle of fiddly proofs change slightly. A common offender involves
tcb_cap_cases, which should be unfolded with the ran_tcb_cap_cases
rule where possible rather than with tcb_cap_cases_def.
2018-08-03 18:25:30 +10:00
Matthew Brecknell a3de401c09 x64: more abstract specs and invariants for ASIDs 2018-07-05 16:23:15 +10:00
Corey Lewis c71fa27e14 Whitespace and typos 2018-07-03 13:42:23 +10:00
Maksym Bortin 9d315cda20 ainvs+refine: update proofs for SetTLSBase (VER-807) 2018-07-03 13:42:19 +10:00
Corey Lewis 967a091cf6 ainvs: Remove unnecessary crunches and whitespace 2018-06-27 11:48:56 +10:00
Corey Lewis 2d0baab462 Proof update for crunch changes 2018-04-04 14:13:55 +10:00
Thomas Sewell 0f38e20094 Many proof repairs. 2018-03-16 14:57:51 +11:00
Thomas Sewell 652cbb966e Initial proof updates for combinator changes. 2018-03-16 14:53:22 +11:00
Joel Beeren 4601f2a1ab Genericise deletion actions that occur after empty_slot
This patch adds a generic "post_cap_deletion" step that is called by
finalise_slot. Previous to this, the only caps which had actions
required at this stage were IRQHandlerCaps -- it was required that the
IRQ bitmap be updated after the cap itself was removed (as the
invariants state that for any existing IRQHandlerCap, the corresponding
bit in the IRQ bitmap must be set).

By genericising this, we add the capacity for new, arch-specific post
cap deletion actions to occur in the future.
2018-02-23 09:12:55 +11:00
Miki Tanaka b37bc04463 arm ainvs: wp rules for simple_ko setter/getter 2017-12-14 18:02:44 +11:00
Joel Beeren a5a5edc832 VER-849: abstractly declare a threads registers have changed
This removes an ifdef present in invokeTCB_(Copy|Write)Registers, and
adds the function Arch_postModifyRegisters which does nothing on any
arch except x86-64.
2017-12-13 12:13:36 +11:00
Rafal Kolanski 3a22487cf3 arm: revise scheduler / fastpath / scheduler bitmaps (SELFOUR-242)
Colloquially known as "invert-fastpath".

Update verification efforts on ARM for the following seL4 changes:
- scheduling decisions done in possibleSwitchTo are moved to the
  scheduler
  - possibleSwitchTo only checks whether the candidate is valid for a
    fast switch, not its priority, accepting possible candidates
    immmediately as a switch-to scheduler action
  - the scheduler checks the candidate against the current thread and
    against the bitmaps before making a decision
  - attemptSwitchTo and switchIfRequiredTo are gone
  - scheduler is now more complicated, and numerous proofs related to it
    are rewritten from scratch
- fast path now checks ready queues via the scheduler bitmaps
- L2 scheduler bitmap order reversed for better cache locality

Many iterations between the kernel and verification teams were needed
to get this right.
2017-11-27 22:05:34 +11:00
Alejandro Gomez-Londono 796887d9b1 Removes all trailing whitespaces 2017-07-12 15:13:51 +10:00
Miki Tanaka 41fe1a0845 update proofs for SELFOUR-30/291 "Reschedule on self-modification"
- SELFOUR-30 Reschedule when changing own IPC buffer
Previously if you invoked the TCB of the current thread and
changed the IPC buffer frame this would not immediately take
affect, as the kernels view of the current IPC buffer is
updated in Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.

- SELFOUR-291 Reschedule when changing own registers
Previously if you wrote to TCB of the current thread and
changed the TLS_BASE this would not immediately take
affect, as the kernel only updates this register in
Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.
2017-06-26 15:52:35 +10:00
Alejandro Gomez-Londono 5aefad5ccf arm-hyp ainvs: fix invariants for make_arch_fault_msg changes 2017-06-19 14:32:29 +10:00
Gerwin Klein 65926a841a arm-hyp/ainvs: proof repair for vgic_maintenance
Includes stronger assumptions for handle_reserved_interrupt and friends,
which should be backported later (see JIRA VER-719 and VER-720)
2017-06-19 14:32:26 +10:00
Joel Beeren 71e2db88a4 arm: refactor sanitise_register to take a bool instead of a kernel_object
This simplified the sanitise_register logic in CRefine for arm-hyp.
2017-05-03 21:51:57 +10:00
Matthew Brecknell 30aa85b0d6 ainvs: strengthen arch assumptions for handle_hypervisor_fault
Contains changes to the generic theory, back-ported and arch-split from
ARM_HYP, as well as corresponding changes to the ARM theory.

Also-by: Gerwin Klein <Gerwin.Klein@data61.csiro.au>
2017-03-14 10:22:25 +11:00
Matthew Brecknell 6ce6c97397 arch_split: DetSchedDomainTime_AI, DetSchedSchedule_AI for ARM 2017-03-09 12:10:44 +11:00
Matthew Brecknell c0c52700fb trivial: rename split_if to if_split following Isabelle2016-1 2017-03-09 11:59:33 +11:00
Miki Tanaka 14aa48bc76 invariant-abstract: updates for Hypervisor stub 2017-02-22 15:26:49 +11:00
Joel Beeren 3dafec7d46 backport changes to ARM proofs from X64 work in progress
- replace ARM-specific constants and types with aliases which can be
  instantiated separately for each architecture.
- expand lib with lemmas used in X64 proofs.
- simplify some proofs.

Also-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2017-01-27 08:31:07 +11:00
Gerwin Klein 47119bf43e wp_cleanup: update proofs for new wp behaviour
The things that usually go wrong:
  - wp fall through: add +, e.g.
      apply (wp select_wp) -> apply (wp select_wp)+

  - precondition: you can remove most hoare_pre, but wpc still needs it, and
    sometimes the wp instance relies on being able to fit a rule to the
    current non-schematic precondition. In that case, use "including no_pre"
    to switch off the automatic hoare_pre application.

  - very rarely there is a schematic postcondition that interferes with the
    new trivial cleanup rules, because the rest of the script assumes some
    specific state afterwards (shouldn't happen in a reasonable proof, but
    not all proofs are reasonable..). In that case, (wp_once ...)+ should
    emulate the old behaviour precisely.
2017-01-13 14:04:15 +01:00
Matthew Brecknell 41d4aa4f1d Isabelle2016-1: update references to renamed constants and facts 2017-01-05 14:23:05 +11:00
Alejandro Gomez-Londono e747996cc6 AInvs: Updating generic theories for tcb_arch reserved_irq and arch_fault
* Rephrasing of all the lemmas that used to refer to tcb_context as
  a direct value on tcb.

* Providing arch-specific lemmas about handle_arch_fault_reply and
  make_arch_fault_msg to deal with handle_fault_reply and make_fault_msg
  new arch-specific cases.

* Trivial but arch-specific proofs about reserved_irq

  tags: [VER-623][SELFOUR-413]
2016-11-25 13:05:55 +11:00
Xin,Gao d7450607a8 SELFOUR-553: rebase and fix styles and comments 2016-11-21 20:47:15 +11:00
Miki Tanaka a2d707d17e SELFOUR-553: update rpidrurw in TCBConfigure for simpler Infoflow proofs. 2016-11-18 16:27:26 +11:00
Miki Tanaka f8f88c6952 SELFOUR-553: Change Spec according to C code and fix ASpec and AInvs 2016-11-18 16:19:14 +11:00
Joel Beeren 2553371a14 SELFOUR-64: Remove general Recycle operation
This removes the RecycleCap CNodeInvocation, whilst
retaining recycle behaviour for Endpoints -- now renamed
CNodeCancelBadgedSends.
2016-11-18 14:11:12 +11:00
Rafal Kolanski 72349f81fd Revert SELFOUR-242: invert bitfield scheduler and optimise fast path
This reverts:
- a67b443ca5
    "SELFOUR-242: update goal number based indentation in Fastpath_C"
- f704cf0404
    "SELFOUR-242: invert bitfield scheduler and optimise fast path"

Verification confirmed functional correctness and refinement of the
system in this case. However, guarantees on thread scheduling and
fairness are not modeled in the current verification. Once this issue is
addressed, SELFOUR-242 will be re-examined.
2016-11-16 14:02:50 +11:00
Rafal Kolanski f704cf0404 SELFOUR-242: invert bitfield scheduler and optimise fast path
* Reverse the level 2 of the bitmap scheduler to move the highest priority
  threads' level 2 entries into the same cache line as the level 1.
* Use the bitfield scheduler to make the fast path a more common occurrence.
* Change possibleSwitchTo to not invoke scheduler when the fast path would not
  invoke it either (using implicit assumptions about the current thread being
  the highest priority schedulable thread)
2016-11-15 09:20:31 +11:00
Rafal Kolanski ff7ca60df7 ADT: add kernel entry/exit constraints on domain time left
These changes to the automatons are required by:
  SELFOUR-242: invert bitfield scheduler and optimise fast path

Details:

When we enter the kernel, the domain time left (ksDomainTime) is never zero.
If we entered on a timer interrupt, we may decrement it to zero before the
scheduler runs. If we do so, we set the scheduler state to choose_new_thread.

When choosing a new thread, the scheduler switches to a new domain if the
present one is required, and sets the new domain time left from domain_list
(ksDomSchedule).

When entering the kernel on a non-interrupt event, we never touch the domain
time left, which trivially preserves the new constraints.

To prove these, we had to ban a transition from kernel entry to kernel being
preempted when handling an interrupt event in InfoFlow. This is fine, as by
design handling interrupts is not meant to be preempted by interrupts.
2016-11-11 06:01:30 +11:00
Matthew Brecknell a3714e8190 SELFOUR-276: Finish proofs for maximum controlled priority (MCP)
To finish the proof of refinement to C, the specification for checkPrio
needed strengthening: the checkPrio spec now takes a machine word
argument. In the spec, priorities are still stored as 8-bit quantities,
however. Once the spec was strenthened, it was possible to remove some
redundant checks and mask operations from the C code.

A thread's maximum controlled priority (MCP) determines the maximum
thread priority or MCP it can assign to another thread (or itself).
2016-10-05 02:43:41 +11:00
Sophie Taylor 20539620f9 SELFOUR-276: Add MCP to specs and invariants
A thread's maximum controlled priority (MCP) determines the maximum
thread priority or MCP it can assign to another thread (or itself).
2016-10-05 02:43:41 +11:00
Xin,Gao 8d4a8eb238 SELFOUR-421: fix coding style 2016-09-22 19:23:28 +10:00