Commit Graph

114 Commits

Author SHA1 Message Date
Edward Pierzchalski c4dc578bc3 Fix up proofs after word lemma moves 2018-10-10 14:15:01 +11:00
Edward Pierzchalski d75740201c Remove pure word lemmas from proof/*
Removes redundant lemmas after moving them up to Word_Lib.
2018-10-10 14:15:00 +11:00
Japheth Lim 18e0d934cc refine: move Orphanage to separate session, RefineOrphanage
Previously, the build system conditionally included Orphanage, but only
when built from run_tests. This meant that a plain ‘isabelle jedit’ or
‘make Refine’ would see a different session definition, resulting in a
slow rebuild.

NB: editing Orphanage now requires -l Refine instead of -l BaseRefine.
2018-10-03 19:47:04 +10:00
Mitchell Buckley 8173a37c2d Updated specs and proofs for SELFOUR-1491: control IRQ triggering on ARM. 2018-09-19 16:18:09 +10:00
Gerwin Klein fa553b8085 aspec/refine: remove redundant captransfer_size definition 2018-08-20 09:06:37 +10:00
Gerwin Klein 9646c3a315 Isabelle2018 arm: Refine 2018-08-20 09:06:36 +10:00
Gerwin Klein 6b9d9d24dd Isabelle2018: new "op x" syntax; now is "(x)"
(result of "isabelle update_op -m <dir>")
2018-08-20 09:06:35 +10:00
Gerwin Klein 011e08458e Isabelle2018: new comment syntax
(result of "isabelle update_comments <dirs>")
2018-08-20 09:06:35 +10:00
Gerwin Klein b5cdf4703f globally use session-qualified imports; add Lib session
Session-qualified imports will be required for Isabelle2018 and help clarify
the structure of sessions in the build tree.

This commit mainly adds a new set of sessions for lib/, including a Lib
session that includes most theories in lib/ and a few separate sessions for
parts that have dependencies beyond CParser or are separate AFP sessions.
The group "lib" collects all lib/ sessions.

As a consequence, other theories should use lib/ theories by session name,
not by path, which in turns means spec and proof sessions should also refer
to each other by session name, not path, to avoid duplicate theory errors in
theory merges later.
2018-08-20 09:06:34 +10:00
Gerwin Klein ead3e6fdc4 aspec: message_info_to_data is mostly arch independent
Factored out msg_label_bits, which is the only architecture specific part.
2018-08-06 11:22:51 +10:00
Matthew Brecknell a3de401c09 x64: more abstract specs and invariants for ASIDs 2018-07-05 16:23:15 +10:00
Maksym Bortin 9d315cda20 ainvs+refine: update proofs for SetTLSBase (VER-807) 2018-07-03 13:42:19 +10:00
Rafal Kolanski 15d6b62040 arm: address setCurrentPD mismatch between abstract/haskell/C
ARM setCurrentPD was recently refactored as part of multi-VM support for
ARM_HYP. The Haskell was updated correctly, and the C was not.
Unfortunately, setCurrentPD was manually redefined in MachineOps.thy for
ARM hiding the change, making the C look correct when it wasn't.

We scrap the second definition of setCurrentPD, load it from the Haskell,
and have an abstract set_current_pd that's a bit simpler to refine down
from.

The proofs are updated for the above change and the update to the C
setCurrentPD that was breaking on KZM.
2018-06-22 11:59:30 +10:00
Corey Lewis c686d6e776 lib: Make Crunch more effective at applying supplied rules 2018-06-08 15:48:32 +10:00
Joel Beeren 1634608453 arm: ioportcontrol: Fixes after adding IOPortControlCaps to x64 2018-04-19 05:27:06 +10:00
Gerwin Klein cf601cb3c6 refine+crefine: update proofs for range check change 2018-04-11 08:05:46 +10:00
Corey Lewis 2d0baab462 Proof update for crunch changes 2018-04-04 14:13:55 +10:00
Thomas Sewell 0f38e20094 Many proof repairs. 2018-03-16 14:57:51 +11:00
Thomas Sewell 652cbb966e Initial proof updates for combinator changes. 2018-03-16 14:53:22 +11:00
Gerwin Klein 2d9de5b9a6 ARM refine: proof update for user_context refactor 2018-03-08 18:41:28 +11:00
Michael Sproul f0795805d1 SELFOUR-1016: fix confused deputy problem when setting priorities 2018-02-26 11:19:43 +11:00
Joel Beeren 4601f2a1ab Genericise deletion actions that occur after empty_slot
This patch adds a generic "post_cap_deletion" step that is called by
finalise_slot. Previous to this, the only caps which had actions
required at this stage were IRQHandlerCaps -- it was required that the
IRQ bitmap be updated after the cap itself was removed (as the
invariants state that for any existing IRQHandlerCap, the corresponding
bit in the IRQ bitmap must be set).

By genericising this, we add the capacity for new, arch-specific post
cap deletion actions to occur in the future.
2018-02-23 09:12:55 +11:00
Joel Beeren 3d225cde69 VER-910: add msgLabelBits to haskell
message_info structs have 20 bit labels. On 32-bit systems, the label
does not need to be masked as there are no extra padding bits in the
struct, but this is not true for 64-bit systems. As a result, the
haskell needs to mask msgLabelBits (=20) when extracting the label in
messageInfoFromWord.
2018-02-07 10:36:59 +11:00
Michael Sproul 995b88cefa SELFOUR-707: schedule highest priority thread on setPriority 2018-01-19 16:08:11 +11:00
Matthew Brecknell 2f540e802c add constant definitions for bounds on untyped object sizes 2017-12-18 12:58:27 +11:00
Miki Tanaka 2a1beffac1 arm: update for simple_ko getter/setter 2017-12-14 18:02:48 +11:00
Miki Tanaka 3841b6e8ba arm : add AEndpoint and ANTFN a_type simplification
in addition to the a_type ATCB simplification, the following two are now in the simpset:
  "a_type (Endpoint x) = AEndpoint"
  "a_type (Notification v) = ANTFN"
2017-12-14 07:17:27 +11:00
Joel Beeren a5a5edc832 VER-849: abstractly declare a threads registers have changed
This removes an ifdef present in invokeTCB_(Copy|Write)Registers, and
adds the function Arch_postModifyRegisters which does nothing on any
arch except x86-64.
2017-12-13 12:13:36 +11:00
Rafal Kolanski 3a22487cf3 arm: revise scheduler / fastpath / scheduler bitmaps (SELFOUR-242)
Colloquially known as "invert-fastpath".

Update verification efforts on ARM for the following seL4 changes:
- scheduling decisions done in possibleSwitchTo are moved to the
  scheduler
  - possibleSwitchTo only checks whether the candidate is valid for a
    fast switch, not its priority, accepting possible candidates
    immmediately as a switch-to scheduler action
  - the scheduler checks the candidate against the current thread and
    against the bitmaps before making a decision
  - attemptSwitchTo and switchIfRequiredTo are gone
  - scheduler is now more complicated, and numerous proofs related to it
    are rewritten from scratch
- fast path now checks ready queues via the scheduler bitmaps
- L2 scheduler bitmap order reversed for better cache locality

Many iterations between the kernel and verification teams were needed
to get this right.
2017-11-27 22:05:34 +11:00
Matthew Brecknell 3cb118fe02 Isabelle2017: update Refine for RC0 2017-10-30 12:23:26 +11:00
Matthew Brecknell 48b3a8b4ca update object and field widths for x64, and remove some magic numbers
In X64 update the following to match the C kernel:
  - TCB size-bits (11).
  - Endpoint size-bits (4).
  - Guard bits (58).
  - Message registers.

For all architectures, replace magic numbers with defined constants in
specifications, and as far as possible in proofs:
  - tcb_bits in abstract spec.
  - tcbBlockSizeBits, cteSizeBits, ntfnSizeBits, epSizeBits in Haskell
    spec, Haskell and C refinement proofs.
2017-10-26 14:05:35 +11:00
Pang Luo 6b9912c47a manually adjust non-obvious cases of tab to space replacement 2017-10-20 14:22:36 +11:00
Matthew Brecknell 184d6b70b7 remove most tab characters 2017-10-20 14:22:36 +11:00
Miki Tanaka 6d8e917087 Remove valid_arch_objs
now that we have valid_vspace_objs to express validiy of
vspace objects, we do not need valid_arch_objs: we have
valid_objs to state the validity of non-vspace arch objects.
2017-08-17 22:44:23 +10:00
Joel Beeren 42401684b0 refine: integrate all architectures 2017-08-09 17:02:49 +10:00
Daniel Matichuk c72bece06f fix ARM Refine for newest corres method after ARM_HYP rebase
VER-737
2017-07-18 12:19:27 -06:00
Daniel Matichuk 2d2f2a1e1d fix refine proofs for improved corres_pre
minor fix - verification condition no longer
generated mid-proof

VER-737
2017-07-17 13:09:46 -06:00
Daniel Matichuk 8c7163457a remove explicit use of corres_rv rules
This is now handled by the corres method

VER-737
2017-07-17 13:09:46 -06:00
Daniel Matichuk 206be43920 use correswp and correct corres_rv rules 2017-07-17 13:09:46 -06:00
Daniel Matichuk fa6112378d cleanup refine for latest corres_method
Some fallout from protecting return-value relations

VER-737
2017-07-17 13:09:08 -06:00
Daniel Matichuk 8d454f1deb use new lift_corres_args attribute to abstract function args
This avoids manually rewriting the lemma statements, but puts
the rules in the more general form
2017-07-17 13:08:19 -06:00
Daniel Matichuk 2bc620c670 addressing protect_r -> corres_protect rename 2017-07-17 13:08:19 -06:00
Daniel Matichuk 196e2e2e0a fix corres proofs for corres method
Fixing the fact that ex_abs is slightly rephrased

VER-737
2017-07-17 13:06:55 -06:00
Daniel Matichuk 9ab936e815 fix refine after changes to corres_method 2017-07-17 12:54:08 -06:00
Alejandro Gomez-Londono 796887d9b1 Removes all trailing whitespaces 2017-07-12 15:13:51 +10:00
Joel Beeren 81064fdb55 idle-thread-pd: run idle thread with the global PD all the time.
This avoids the multicore scenario of the idle thread running in the
address space that has been deleted by a thread running on another core.
2017-07-11 11:29:34 +10:00
Miki Tanaka 41fe1a0845 update proofs for SELFOUR-30/291 "Reschedule on self-modification"
- SELFOUR-30 Reschedule when changing own IPC buffer
Previously if you invoked the TCB of the current thread and
changed the IPC buffer frame this would not immediately take
affect, as the kernels view of the current IPC buffer is
updated in Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.

- SELFOUR-291 Reschedule when changing own registers
Previously if you wrote to TCB of the current thread and
changed the TLS_BASE this would not immediately take
affect, as the kernel only updates this register in
Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.
2017-06-26 15:52:35 +10:00
Joel Beeren 392d055e99 SELFOUR-748: rename tlb invalidation functions 2017-06-20 14:05:45 +10:00
Alejandro Gomez-Londono 2d20221396 arm refine: updates for the backport from arm-hyp completed 2017-06-19 14:32:44 +10:00
Alejandro Gomez-Londono b76709967b arm refine: Updating theories for ainvs changes 2017-06-19 14:32:44 +10:00
Pang Luo da28d94974 VER-717: refactor tpidrurwRegister and fix corresponding proof 2017-05-05 15:17:41 +10:00
Joel Beeren 71e2db88a4 arm: refactor sanitise_register to take a bool instead of a kernel_object
This simplified the sanitise_register logic in CRefine for arm-hyp.
2017-05-03 21:51:57 +10:00
Daniel Matichuk df7693b687 refinement refactor: up to resolve_address_bits
Proofs have been refactored to use new corres methods, including
marking rules with the [corres] attribute so they are automatically
applied.

VER-737
2017-03-28 22:37:34 +11:00
Gerwin Klein 4620f7622f refine ARM: minor cleanup 2017-03-17 15:14:41 +11:00
Miki Tanaka 7ad3ef3b3e wp: update the proofs for the new wp/wpc/wpsimp 2017-03-16 19:39:11 +11:00
Matthew Brecknell 6ce6c97397 arch_split: DetSchedDomainTime_AI, DetSchedSchedule_AI for ARM 2017-03-09 12:10:44 +11:00
Matthew Brecknell c0c52700fb trivial: rename split_if to if_split following Isabelle2016-1 2017-03-09 11:59:33 +11:00
Gerwin Klein 99c7dd8a04 cleanup: remove old wp_cleanup comments 2017-03-03 09:01:28 +11:00
Gerwin Klein 8a7d450f3a ainvs + refine: remove hv_inv_ex
The lemma was convenient, but is subsumed by others. It is not true on
ARM_HYP.
2017-03-02 10:26:10 +11:00
Miki Tanaka 2699254382 Refine: updates for Hypervisor stub 2017-02-22 15:26:49 +11:00
Miki Tanaka 3db5dd778d Refine fix for prepare_thread_delete 2017-02-20 09:23:55 +11:00
Daniel Matichuk 2ac4fa3509 corres_method: use corres method by default 2017-02-15 15:00:23 +11:00
Gerwin Klein 520921351a provide TCB argument for sanitiseRegister
Other platforms such as arm-hyp will need to look into additional TCB state
such as VCPU in sanitiseRegister. This commit provides the scaffolding for
that.
2017-02-12 12:54:42 +11:00
Rafal Kolanski 7657681fca move refine/* to refine/ARM/*, parametrise over $L4V_ARCH 2017-01-30 12:22:22 +11:00