Commit Graph

11 Commits

Author SHA1 Message Date
Corey Lewis 008969fc02 lib proof: reorder the assumptions of corres_split
Currently this just modifies the rule but not any of the proofs that use
it. The old version is kept for now but should be removed once all of
the proofs are updated.

Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-02-19 11:37:12 +11:00
Gerwin Klein 81117dc587 riscv cleanup: remove stray diagnostic commands
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 71e7f87614 haskell/refine/crefine: rename isBlocked to isStopped
sync with corresponding change in C

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-05-06 15:49:02 +10:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Victor Phan 966734c69b Collect abstract lemmas in Refine
Create ArchMove_R.thy for transporting arch specific lemmas (and generic
lemmas that are used somewhat specifically by one architecture) to theory
files before Refine.

Create Move_R.thy as an arch generic Refine theory file for transporting
generic lemmas to theory files before Refine.

Also delete some lemmas that have existed earlier already or are not
needed.

Rename Move.thy in CRefine to Move_C.thy for consistency.
2020-02-21 11:49:25 +11:00
Victor Phan f2d1f5ada7 refine/crefine: convert crunch with multiple constants into crunches 2020-02-03 16:29:19 +11:00
Victor Phan 285c47f622 cleanup for crunch_ignore in refine and crefine for all arches
Several constants are are added to the top level crunch_ignore statement in
Bits_R.thy, then removed from individual crunch statements across Refine and
CRefine.
2020-02-03 16:29:18 +11:00
Gerwin Klein 01c6c9f7b5 riscv refine: weaken precondition of threadSet_invs_trivialT 2019-11-12 18:28:39 +11:00
Gerwin Klein e850ab5ea5 riscv refine: reduce Haskell guards in TcbAcc 2019-11-12 18:28:39 +11:00
Gerwin Klein e25631e919 riscv refine: more guard cross-over rules 2019-11-12 18:28:39 +11:00
Gerwin Klein 7fde8b47a0 riscv refine: set up TcbAcc_R (0 sorries) 2019-11-12 18:28:39 +11:00