Commit Graph

3712 Commits

Author SHA1 Message Date
Rafal Kolanski 57b8f451b1 riscv ainvs: prove set_asid_pool_vs_lookup_unmap' 2019-07-31 16:55:32 +10:00
Rafal Kolanski f52c70af73 riscv ainvs: valid_vspace_objs over non-PTPTE store_pte
Weakened rules specific to InvalidPTE, showed
store_pte_PagePTE_valid_vspace_objs
2019-07-31 16:55:32 +10:00
Gerwin Klein a252e040e4 riscv ainvs: prove perform_asid_pool_invs
This includes various lemmas on copy_global_mappings.
2019-07-31 16:55:32 +10:00
Gerwin Klein 0122b80dc5 riscv ainvs: improve ex_vs_lookup_table notation
Should now contract.
2019-07-31 16:55:32 +10:00
Rafal Kolanski 0f8d69a029 riscv ainvs: idempotency of lookups over unreachable updates
If there is no way to look up a vspace object, then changing it cannot
affect existing lookup paths.
2019-07-31 16:55:32 +10:00
Rafal Kolanski 2901899cc8 riscv ainvs: more invariant preservation over store_pte
shown preservation of:
valid_table_caps
valid_global_tables
valid_global_arch_objs
unique_table_refs
unique_table_caps
valid_asid_pool_caps
2019-07-31 16:55:32 +10:00
Rafal Kolanski 7409acb3e6 riscv ainvs: lift some set_pt properties to store_pte 2019-07-31 16:55:32 +10:00
Gerwin Klein 744a85c311 riscv ainvs: remove simple sorries ArchArch_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 6448a3c47d riscv ainvs: clean out invariants and preconditions on ASID size
These are now already enforced by type.
2019-07-31 16:55:32 +10:00
Gerwin Klein 75efc6a90c riscv ainvs: remove 3 sorries ArchVSpace_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 116009c1d7 riscv aspec: constrain asid type to asid_len
We previously had asids at machine word representation, but it turns out that
constraining them to actual asid_len is almost no overhead and saves us proving
invariants about asid sizes.
2019-07-31 16:55:32 +10:00
Gerwin Klein bb7062c263 riscv ainvs: clear out 7 sorries about replacable caps in ArchFinalise
(plus removal of one unused lemma)
2019-07-31 16:55:32 +10:00
Gerwin Klein d6a5b3c983 riscv ainvs: wellformed_mapdata more RISCV-idiomatic
use "vref : user_region", instead of pptr_base and canonical_address, which
was more an X64 idiom
2019-07-31 16:55:32 +10:00
Gerwin Klein f90a9d1080 riscv ainvs: close one sorry in ArchVSpace_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 6c3fb3a1cb riscv ainvs: removed two unused lemmas (and sorries) 2019-07-31 16:55:32 +10:00
Gerwin Klein d140b5d9bc aspec: workaround for VER-1099
(locale_abbrev does not always contract when part of the abbreviation chain is outside the locale)
2019-07-31 16:55:32 +10:00
Rafal Kolanski 406a3eb9b4 riscv ainvs: idempotency of vs_lookup_table over kheap update
When we look up a vref and reach a page table / asid pool, it could not
have been used in the lookup and hence changing it has no effect on the
lookup.
2019-07-31 16:55:32 +10:00
Rafal Kolanski 212ea6724a lib: add obind_eqI_full to OptionMonad
Sometimes after showing equality of the heads of the obind, we need this
result in proof of equality of the tails.
2019-07-31 16:55:32 +10:00
Rafal Kolanski 8db6a74716 riscv ainvs: clear unneeded is_aligned from pt_walk_eqI up 2019-07-31 16:55:32 +10:00
Gerwin Klein a893a40aa5 riscv ainvs: reduce sorries in ArchVSpace_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 8fb9aa8b91 riscv ainvs: reduce sorries in ArchVSpace_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 1b9a7d3174 riscv ainvs: more automatic atyp_at lifting; vs_ap_ref_arch_simps 2019-07-31 16:55:32 +10:00
Gerwin Klein a88891ea7c riscv ainvs: adjustments for is_valid_vtable root spec fix 2019-07-31 16:55:32 +10:00
Gerwin Klein ed87ba03a9 riscv aspec: vtable roots must be page table caps 2019-07-31 16:55:32 +10:00
Gerwin Klein c386d2a85e riscv ainvs: remove trivial sorry in ArchVSpace_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 2f2b7b0c7f riscv ainvs: ArchRetype_AI sorry-free 2019-07-31 16:55:32 +10:00
Gerwin Klein 298445c347 riscv ainvs: update ArchKernelInit_AI for user_region refactor 2019-07-31 16:55:32 +10:00
Gerwin Klein 3171901efd riscv ainvs: -1 sorry in ArchRetype_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein cd49720dbe riscv ainvs: refactor user_region to be state-independent
This refactoring makes user_region statically equal to {0 .. canonical_user},
which removes the need for a valid_uses s precondition in most lemmas about
user_region, which is needed for the generic/architecture interface in
ArchRetype_AI.

To express that this is equivalent with the old concept, there is a new
"user_window s", which under valid_uses, is the same set as user_region, but
demands that memory uses are correctly set to RISCVVSpaceUserRegion.
2019-07-31 16:55:32 +10:00
Gerwin Klein 04926d48e4 riscv ainvs: clean-up (comment addressed in ArchAInvsPre) 2019-07-31 16:55:32 +10:00
Rafal Kolanski 30bda7cdc4 riscv ainvs: reduce sorries in ArchFinalise_AI 2019-07-31 16:55:32 +10:00
Rafal Kolanski b27fa1e41e riscv ainvs: reduce sorries in ArchAcc_AI 2019-07-31 16:55:32 +10:00
Rafal Kolanski 2b359f6265 riscv ainvs: typos: canoncial->canonical 2019-07-31 16:55:32 +10:00
Rafal Kolanski 89aafed912 riscv aspec+ainvs+haskell: update kernelBase, paddrLoad to match C
update for changeset 897aaf5b13f39ba2b9ca8ade3a58d1350eb42ad7

This changes properties of kernel_base, thereby invalidating two unused
lemmas: mask_out_8_le_kernel_base, mask_out_8_less_kernel_base
2019-07-31 16:55:32 +10:00
Rafal Kolanski 96b3876ad1 riscv ainvs: complete level uniqueness proof
ex_vs_lookup_level shows we can't find the same table/pool at different
lookup depths; combined with unique_vs_lookup_table we can now show that
there exists only one lookup path from the ASID table to any table/pool
object in the system
2019-07-31 16:55:32 +10:00
Rafal Kolanski 240302d89b riscv ainvs: complete proof of no_loop_vs_lookup_table
Long-running joint work with Gerwin Klein.

This lemma demonstrates that from our invariants, when looking up two virtual
addresses in the same ASID, if lookups end up at the same page table, then
the page table must be found at the same level, disallowing loops in
either of the lookups.
2019-07-31 16:55:32 +10:00
Gerwin Klein b2600af6ec riscv ainvs: -2 sorries in ArchRetype_AI 2019-07-31 16:55:32 +10:00
Gerwin Klein 439b56eb11 riscv ainvs: adjust for pt_walk_0[simp] 2019-07-31 16:55:32 +10:00
Rafal Kolanski 5b0aa53836 riscv ainvs: add and migrate lemmas to ArchInvariants_AI
Adds properties of:
- vm_levels
- ptrFromPAddr alignment
- alignment of lookup/walk results

Some other lemmas migrated from ArchAcc_AI.
2019-07-31 16:55:31 +10:00
Rafal Kolanski f3d95dbb8f Word_Lib: add masking lemmas from RISCV64 lookup proofs 2019-07-31 16:55:31 +10:00
Rafal Kolanski 0296b241c8 riscv ainvs: generalise pt_slot_offset_vref/pt_slot_offset_vref_for_level_eq
Apply to any higher level rather than only max_pt_level.
2019-07-31 16:55:31 +10:00
Gerwin Klein 223b41dbfa riscv ainvs: -2 sorries in ArchRetype_AI 2019-07-31 16:55:31 +10:00
Gerwin Klein f774c6cc27 riscv ainvs: ArchVSpaceEntries_AI sorry-free 2019-07-31 16:55:31 +10:00
Rafal Kolanski 05b547c8bf riscv ainvs: change pte to store ppn instead of address
We preserve the functionality of pte_info by converting the ppn to an address.
2019-07-31 16:55:31 +10:00
Rafal Kolanski 8cd2f3de79 riscv aspec: change pte to store ppn instead of address
On other architectures, the address is a PTE stored using field_high and
thus retrieved as an aligned address. On RISCV we have a frame number
(referred to as PPN in some places) that is the address shifted down by
pt_bits.

This changes over the pte to use a ppn with a different number of bits,
and provides addr_from_ppn and addr_from_pte accessors, the latter being
an abbreviation.

Issues:
- "ppn" and "frame" show up in C, which should we use
- conversion functions take paddr, but are named with "addr": change
  naming to use paddr?
- we sanity check the number of bits in a ppn is word_bits - pt_bits,
  but in C that number subtracts another 8 bits, not clear why
2019-07-31 16:55:31 +10:00
Rafal Kolanski 745b7d1863 riscv ainvs: update comment for vs_lookup_InvalidPTE proof 2019-07-31 16:55:31 +10:00
Gerwin Klein 73aa8c85e4 ainvs: adjust to new None_upd_eq[simp] context 2019-07-31 16:55:31 +10:00
Gerwin Klein 7a4d5b1ea9 lib: general update lemmas for opt_map 2019-07-31 16:55:31 +10:00
Gerwin Klein 4112cae517 riscv ainvs: remove last numerical mentions of asid_high/low bits 2019-07-31 16:55:31 +10:00
Rafal Kolanski 341d12d2fb riscv aspec: adjust asid high and low bits to match C
1 bit moves from high bits to low bits
2019-07-31 16:55:31 +10:00