Commit Graph

1358 Commits

Author SHA1 Message Date
Michael Sproul 2151a57c51 x64: crefine: move two lemmas up to CSpaceAcc_C 2018-08-17 15:41:12 +10:00
Michael Sproul 4ddf8ec2e4 x64: crefine: remove needless `unwrap_or` def 2018-08-17 15:41:12 +10:00
Gerwin Klein 9a4d2677e3 lib+spec: move definition of machine_word to Word_Lib
JIRA VER-963
2018-08-06 11:22:52 +10:00
Gerwin Klein 5ae7cc23b1 aspec: msg_align_bits and related are arch independent
While the numerical value is arch dependent, the definition and symbolic value
are not. This commit factors out the symbolic computation and only unfolds the
numeric value in the architecture dependent spec.
2018-08-06 11:22:51 +10:00
Gerwin Klein ead3e6fdc4 aspec: message_info_to_data is mostly arch independent
Factored out msg_label_bits, which is the only architecture specific part.
2018-08-06 11:22:51 +10:00
Gerwin Klein 8f1122270c aspec/ainvs: move TLS/ipc buffer FIXME to appropriate position in ADT_AI 2018-08-06 11:22:49 +10:00
Thomas Sewell 26049db669 Repair proofs for wpsimp/crunch changes.
A handle of fiddly proofs change slightly. A common offender involves
tcb_cap_cases, which should be unfolded with the ran_tcb_cap_cases
rule where possible rather than with tcb_cap_cases_def.
2018-08-03 18:25:30 +10:00
Japheth Lim 8392624f6c infoflow: hacky speedups for Noninterference.thy
This speeds up a bunch of the slowest uwr and automaton proofs in
Noninterference, mainly by adjusting the simp depth limit to avoid
unneeded backtracking. Inspired by a rant from Tom Sewell.
2018-08-02 16:53:04 +10:00
Japheth Lim 31737df065 infoflow: improve header comment for Noninterference.thy 2018-08-02 16:53:04 +10:00
Japheth Lim 166af9e5ee access, infoflow: cleanup from previous commit; some style cleanup 2018-08-02 16:53:04 +10:00
Japheth Lim a6c11a2b28 access-control, infoflow: use generic relation for pasDomainAbs
This patch generalises the mapping between authority labels and
scheduler domains, so that the access-control integrity property still
holds when labels are not partitioned into domains. This lets us use
the integrity result on systems that don't use the domain scheduler.

The information flow proofs still rely on the domain partitioning,
hence we add constraints on the label-domain mapping for the info-flow
results to hold.

Jira VER-945
2018-08-02 15:01:42 +10:00
Thomas Sewell f3957348e8 proof/Makefile: add SimplExport* dependencies
Add the design-spec dependency to the SimplExport* targets, since the
haskell conversion needs to be done to create the MachineTypes theory
before the CKernel image can be created.
2018-07-24 11:38:40 +10:00
Thibaut Perami 9523eea0d6 infoflow: Clean up infoflow, comment, wrap lines, ... 2018-07-16 15:36:21 +10:00
Rafal Kolanski 9e0551f56a arm-hyp: update proofs for TPIDRUR[OW]/TLS_BASE preservation
TPIDRUR[OW] registers removed from VCPU registers. Their saving now
lives in arch_c_entry_hook, which is before verified code is hit.

Relevant for verification, TPIDRURO is already handled as TLS_BASE
register, and TPIDRURW (holds IPC buffer) is saved/restored as part of
normal thread register save/restore.
2018-07-12 23:38:58 +10:00
Michael Sproul e11abb6011 x64: crefine: prove isIOPortRangeFree_spec 2018-07-05 17:07:58 +10:00
Matthew Brecknell 80693df8e2 x64 crefine: add mask_eq_ucast_shiftl 2018-07-05 17:07:58 +10:00
Matthew Brecknell 3231ee17bf x64 crefine: prove 'return false' case of isIOPortRangeFree_spec postcondition 2018-07-05 17:07:58 +10:00
Matthew Brecknell aabf8ded2e x64 crefine: progress on isIOPortRangeFree_spec postcondition 2018-07-05 17:07:58 +10:00
Joel Beeren 7eb8e01443 x64: crefine: proved word_highbits_bounded_highbits_eq
Contributed by: Michael Sproul <michael.sproul@data61.csiro.au>
2018-07-05 17:07:57 +10:00
Joel Beeren da05f4f72e x64: crefine: cleared vcg precondition sorry in isIOPortRangeFree_spec, modulo small word lemma 2018-07-05 17:07:57 +10:00
Matthew Brecknell b9c3279779 x64 crefine: prove mask_le_mono
Contributed by: Thomas Sewell <Thomas.Sewell@data61.csiro.au>
2018-07-05 17:07:57 +10:00
Matthew Brecknell 7a951cad95 x64 crefine: prove invariant preservation for isIOPortRangeFree_spec 2018-07-05 17:07:49 +10:00
Michael Sproul 7af93e5bc1 x64: crefine: prove word_minus_1_shiftr 2018-07-05 16:23:15 +10:00
Joel Beeren 07b60ec185 x64: crefine: progress on sorries in isIOPortRangeFree_spec 2018-07-05 16:23:15 +10:00
Matthew Brecknell f0a8621434 x64 crefine: prove isIOPortRangeFree_ccorres in Arch_C (WIP) 2018-07-05 16:23:15 +10:00
Gerwin Klein 91b55bc74b x64 crefine: progress on spec and inv for isIOPortRangeFree 2018-07-05 16:23:15 +10:00
Matthew Brecknell 74e74571ca x64 crefine: prove setIOPortMask_ccorres in CSpace_C 2018-07-05 16:23:15 +10:00
Michael Sproul 72e3dcc8e2 x64: crefine: prove decodeX64MMUInvocation_ccorres
Required adding a case to cl_valid_cap to encode the relationship between a
PML4Cap's IsMapped bit and its MappedASID.
2018-07-05 16:23:15 +10:00
Joel Beeren 0f0f46b2b0 x64: refine: fix fallout from decodeX64PageInvocation change 2018-07-05 16:23:15 +10:00
Joel Beeren 5ce7ed478f x64: crefine: add SetTLSBase invocation to x64 CRefine 2018-07-05 16:23:15 +10:00
Joel Beeren 2558a7c6e5 x64: crefine: update decodeX64FrameInvocation to not mask with PPTR_USER_TOP 2018-07-05 16:23:15 +10:00
Joel Beeren 89df98ec14 x64: fix inadvertently broken lemma in CSpace_C 2018-07-05 16:23:15 +10:00
Joel Beeren 417e6b8bc1 arm-hyp: crefine: fix up eisr_calc proof for strengthened ccorres_rewrite 2018-07-05 16:23:15 +10:00
Joel Beeren 584c6e9d26 x64: crefine: prove decodeX64FrameInvocation_ccorres 2018-07-05 16:23:15 +10:00
Joel Beeren 7f52da6571 x64: ainvs+refine: fix up proofs for decodeX64FrameInvocation changes 2018-07-05 16:23:15 +10:00
Joel Beeren 5ed7bb16be x64: fix up definition of performPageInvocation for unmapping pages 2018-07-05 16:23:15 +10:00
Matthew Brecknell 700060b642 x64 crefine: prove Arch_decodeInvocation_ccorres in Arch_C 2018-07-05 16:23:15 +10:00
Matthew Brecknell 047f96c711 x64 crefine: prove kernel_mappings conditions in Retype_C 2018-07-05 16:23:15 +10:00
Matthew Brecknell 3686d79677 x64 crefine: prove createObjects_asidpool_ccorres in Arch_C
In x64, asid_map_C is now a bitfield union type, whereas in ARM,
the ASID pool contains plain pointers. This means that proving
ccorres for the x64 ASID pool placeNewObject operation requires
some additional unfolding of C type information.
2018-07-05 16:23:15 +10:00
Matthew Brecknell c390013909 x64 crefine: prove several lemmas in Retype_C
To prove that retyping a TCB establishes the state relation for TCBs,
it is necessary to prove that the C FPU null state is always equal to
the Haskell FPU null state. This commit therefore includes some
machinery for maintaining the state relation for the FPU null state,
and repairs many proofs.
2018-07-05 16:23:15 +10:00
Michael Sproul 26b218e4bd x64: crefine: clear sorries for decode PT/PD/PDPT 2018-07-05 16:23:15 +10:00
Joel Beeren 151ca60b9f x64: refine: add new invariant "pspace_in_kernel_mappings'"
This invariant shows that all pointers in ksPSpace are above pptr_base -
that is, in the kernel window. This was never formally proven before, as
had never truly been required (although it is true).
2018-07-05 16:23:15 +10:00
Joel Beeren 0bad7af88b x64: crefine: actually clear last ioport_table_C sorry 2018-07-05 16:23:15 +10:00
Joel Beeren 1dea36ed6f x64: crefine: add some tag disjunctions for ioport_table_C to SR_Lemmas_C 2018-07-05 16:23:15 +10:00
Joel Beeren bcd21f27bf x64: crefine: clear final two sorries from ioport_bitmap_relation fallout 2018-07-05 16:23:15 +10:00
Joel Beeren d6a620ec5d x64: crefine: move setIOPortMask_ccorres to CSpace_C, finish freeIOPortRange_ccorres 2018-07-05 16:23:15 +10:00
Joel Beeren 3c65b91512 x64: crefine: finished invokeX86PortControl_ccorres and decodeIOPortControlInvocation_ccorres 2018-07-05 16:23:15 +10:00
Joel Beeren d487d1fc6a x64: crefine: added ioport bitmap to StateRelation_C 2018-07-05 16:23:15 +10:00
Joel Beeren 95cdaa8ad7 x64: crefine: cleared sorry in decodeIOPortInvocation_ccorres 2018-07-05 16:23:15 +10:00
Michael Sproul cf1052e303 x64: crefine: prove prepareThreadDelete_ccorres (VER-837) 2018-07-05 16:23:15 +10:00