Commit Graph

154 Commits

Author SHA1 Message Date
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Gerwin Klein 8d12d8e4be licenses: tag .md and document file 2020-03-02 18:52:15 +08:00
Gerwin Klein 0ed60666e3 drefine: invocation label proof updates 2020-02-03 12:56:19 +08:00
Victor Phan b9c285400d remove diminished (VER-1158)
diminished takes two caps and asserts that one is equal to the other
except that one may have fewer rights. We remove this definition and all
references to it, replacing diminished with equality.
2019-11-16 01:03:36 +11:00
Gerwin Klein c390ba7404 proofs: adjustments for word_lib changes 2019-11-15 12:08:22 +11:00
Corey Lewis 9846cd42bb proof: update for crunch changes 2019-10-14 17:23:41 +11:00
Corey Lewis dd48e0d899 proof: update for wp changes
Updated 'wp_once' to 'wp (once)' and removed several stray uses of 'wp_trace'.
2019-10-14 17:12:18 +11:00
Victor Phan 9938dd39da drefine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-10-10 11:27:28 +11:00
MiladKetabi acbc08b836 clean-ups done during proof update for the jira issue SELFOUR-1187: seL4 setPriority should attempt a direct schedule 2019-10-06 18:31:19 +11:00
MiladKetabi d934d25269 proof update for SELFOUR-1187: seL4 setPriority should attempt a direct schedule
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.
2019-10-06 18:31:19 +11:00
Gerwin Klein d7bce104a7 drefine: adjust for arch-decode interface strengthening 2019-07-31 16:55:32 +10:00
Amirreza Zarrabi 178f6d055f drefine: remove arch_tcb_set_ipc_buffer and updates for the change 2019-06-28 11:48:47 +10:00
Gerwin Klein c34840d09b global: isabelle update_cartouches 2019-06-14 11:41:21 +10:00
Michael McInerney 356e91c9fa access-control, capDL-api, drefine, infoflow, sep-capDL, capDL: update for Isabelle2019 2019-06-13 16:22:33 +10:00
Michael McInerney 4463e9750e SELFOUR-1198: update proofs for correct restart PC
Fixes a case where a thread can go from Running->Inactive->Restart and
use a restart PC that is out of date. An out of date restart PC occurs
when a thread was transitioned to running after being in a blocked
state, but was never scheduled and so did not execute the traps code
that updates the restart PC.

This also renames relevant register names for consistency across
architectures (FaultIP and NextIP).
2019-06-13 11:43:50 +10:00
Victor Phan 1689dd94fe cleanup
arm ainvs: cleanup

Abbreviate Hoare triples that do not care about the return value and
whose pre and post conditions are the same.

x64 ainvs: cleanup

ainvs: cleanup

x64 ainvs: cleanup

drefine: cleanup
2019-04-18 14:32:08 +10:00
Victor Phan d93eb12b7f drefine: update for new definition of set_object 2019-04-18 14:32:08 +10:00
Michael Sproul c44fd87594 capdl: remove redundant definition `opt_object`
A lot of the proofs in SysInit and DRefine previously had to unfold opt_object,
which was really just an alias for cdl_objects with the arguments in the
opposite order! This commit deletes opt_object in favour of using cdl_objects
directly, which should slightly reduce the burden of unfolding.
2019-02-28 14:34:01 +11:00
Japheth Lim 3758df05df dspec, drefine: fix for GrantReply (SELFOUR-6)
Nothing too exciting here, just duplicating the new GrantReply logic
from ASpec and repairing the proofs.
2018-12-10 20:01:38 +11:00
Santiago Bautista ab259704c7 access+infoflow+drefine: update for new definition of `idle_tcb_at`
* Context :

 We would like to prove that, for ARM_HYP architecture,
  the current vcpu is always the vcpu associated to the current thread.
 See issue https://jira.csiro.au/browse/VER-770
  and PR 291 http://bitbucket.keg.ertos.in.nicta.com.au/projects/SEL4/repos/l4v/pull-requests/291

 In this process, we changed the definition of `idle_tcb_at`

* In this commit :

 Update some proofs in access, infoflow and drefine to take
  the new definition of `idle_tcb_at` into account.
2018-10-31 18:04:59 +11:00
Gerwin Klein 15bfcdd98b reduce DRefine dependencies from Refine to AInvs
This needs (and includes) some deduplication and moving of lemmas formerly in
refine.
2018-10-22 13:21:11 +11:00
Edward Pierzchalski c4dc578bc3 Fix up proofs after word lemma moves 2018-10-10 14:15:01 +11:00
Mitchell Buckley 8173a37c2d Updated specs and proofs for SELFOUR-1491: control IRQ triggering on ARM. 2018-09-19 16:18:09 +10:00
Gerwin Klein 1e8a7505ef Isabelle2018: DRefine 2018-08-20 09:06:36 +10:00
Gerwin Klein 6b9d9d24dd Isabelle2018: new "op x" syntax; now is "(x)"
(result of "isabelle update_op -m <dir>")
2018-08-20 09:06:35 +10:00
Gerwin Klein 011e08458e Isabelle2018: new comment syntax
(result of "isabelle update_comments <dirs>")
2018-08-20 09:06:35 +10:00
Gerwin Klein b5cdf4703f globally use session-qualified imports; add Lib session
Session-qualified imports will be required for Isabelle2018 and help clarify
the structure of sessions in the build tree.

This commit mainly adds a new set of sessions for lib/, including a Lib
session that includes most theories in lib/ and a few separate sessions for
parts that have dependencies beyond CParser or are separate AFP sessions.
The group "lib" collects all lib/ sessions.

As a consequence, other theories should use lib/ theories by session name,
not by path, which in turns means spec and proof sessions should also refer
to each other by session name, not path, to avoid duplicate theory errors in
theory merges later.
2018-08-20 09:06:34 +10:00
Gerwin Klein 5ae7cc23b1 aspec: msg_align_bits and related are arch independent
While the numerical value is arch dependent, the definition and symbolic value
are not. This commit factors out the symbolic computation and only unfolds the
numeric value in the architecture dependent spec.
2018-08-06 11:22:51 +10:00
Gerwin Klein ead3e6fdc4 aspec: message_info_to_data is mostly arch independent
Factored out msg_label_bits, which is the only architecture specific part.
2018-08-06 11:22:51 +10:00
Thomas Sewell 26049db669 Repair proofs for wpsimp/crunch changes.
A handle of fiddly proofs change slightly. A common offender involves
tcb_cap_cases, which should be unfolded with the ran_tcb_cap_cases
rule where possible rather than with tcb_cap_cases_def.
2018-08-03 18:25:30 +10:00
Matthew Brecknell a3de401c09 x64: more abstract specs and invariants for ASIDs 2018-07-05 16:23:15 +10:00
Corey Lewis c71fa27e14 Whitespace and typos 2018-07-03 13:42:23 +10:00
Corey Lewis 571ef6d0ca crefine+drefine+access+infoflow: update proofs for SetTLSBase (VER-807) 2018-07-03 13:42:22 +10:00
Rafal Kolanski 15d6b62040 arm: address setCurrentPD mismatch between abstract/haskell/C
ARM setCurrentPD was recently refactored as part of multi-VM support for
ARM_HYP. The Haskell was updated correctly, and the C was not.
Unfortunately, setCurrentPD was manually redefined in MachineOps.thy for
ARM hiding the change, making the C look correct when it wasn't.

We scrap the second definition of setCurrentPD, load it from the Haskell,
and have an abstract set_current_pd that's a bit simpler to refine down
from.

The proofs are updated for the above change and the update to the C
setCurrentPD that was breaking on KZM.
2018-06-22 11:59:30 +10:00
Joel Beeren 1634608453 arm: ioportcontrol: Fixes after adding IOPortControlCaps to x64 2018-04-19 05:27:06 +10:00
Corey Lewis 2d0baab462 Proof update for crunch changes 2018-04-04 14:13:55 +10:00
Thomas Sewell 0f38e20094 Many proof repairs. 2018-03-16 14:57:51 +11:00
Thomas Sewell 652cbb966e Initial proof updates for combinator changes. 2018-03-16 14:53:22 +11:00
Gerwin Klein b0cac3ec77 ARM drefine: proof update for user_context refactor 2018-03-08 18:41:28 +11:00
Michael Sproul f0795805d1 SELFOUR-1016: fix confused deputy problem when setting priorities 2018-02-26 11:19:43 +11:00
Joel Beeren 4601f2a1ab Genericise deletion actions that occur after empty_slot
This patch adds a generic "post_cap_deletion" step that is called by
finalise_slot. Previous to this, the only caps which had actions
required at this stage were IRQHandlerCaps -- it was required that the
IRQ bitmap be updated after the cap itself was removed (as the
invariants state that for any existing IRQHandlerCap, the corresponding
bit in the IRQ bitmap must be set).

By genericising this, we add the capacity for new, arch-specific post
cap deletion actions to occur in the future.
2018-02-23 09:12:55 +11:00
Joel Beeren 3d225cde69 VER-910: add msgLabelBits to haskell
message_info structs have 20 bit labels. On 32-bit systems, the label
does not need to be masked as there are no extra padding bits in the
struct, but this is not true for 64-bit systems. As a result, the
haskell needs to mask msgLabelBits (=20) when extracting the label in
messageInfoFromWord.
2018-02-07 10:36:59 +11:00
Matthew Brecknell 2f540e802c add constant definitions for bounds on untyped object sizes 2017-12-18 12:58:27 +11:00
Miki Tanaka 2a1beffac1 arm: update for simple_ko getter/setter 2017-12-14 18:02:48 +11:00
Miki Tanaka 3841b6e8ba arm : add AEndpoint and ANTFN a_type simplification
in addition to the a_type ATCB simplification, the following two are now in the simpset:
  "a_type (Endpoint x) = AEndpoint"
  "a_type (Notification v) = ANTFN"
2017-12-14 07:17:27 +11:00
Joel Beeren a5a5edc832 VER-849: abstractly declare a threads registers have changed
This removes an ifdef present in invokeTCB_(Copy|Write)Registers, and
adds the function Arch_postModifyRegisters which does nothing on any
arch except x86-64.
2017-12-13 12:13:36 +11:00
Rafal Kolanski 3a22487cf3 arm: revise scheduler / fastpath / scheduler bitmaps (SELFOUR-242)
Colloquially known as "invert-fastpath".

Update verification efforts on ARM for the following seL4 changes:
- scheduling decisions done in possibleSwitchTo are moved to the
  scheduler
  - possibleSwitchTo only checks whether the candidate is valid for a
    fast switch, not its priority, accepting possible candidates
    immmediately as a switch-to scheduler action
  - the scheduler checks the candidate against the current thread and
    against the bitmaps before making a decision
  - attemptSwitchTo and switchIfRequiredTo are gone
  - scheduler is now more complicated, and numerous proofs related to it
    are rewritten from scratch
- fast path now checks ready queues via the scheduler bitmaps
- L2 scheduler bitmap order reversed for better cache locality

Many iterations between the kernel and verification teams were needed
to get this right.
2017-11-27 22:05:34 +11:00
Matthew Brecknell d48c211ac9 Isabelle2017: update DRefine (ARM) for RC0 2017-10-30 12:23:26 +11:00
Thomas Sewell 6529c7dd42 Repair schedule_bcorres.
This was broken a long while back because arch_switch_to_idle_thread
might sometimes be skipped in the implementation if the idle thread
was previously scheduled. Putting the same behaviour in the most
abstract (unit) specification is pretty easy, and it's not clear why
it wasn't done earlier.
2017-10-10 11:02:19 +11:00
Matthew Brecknell b8fc532b4e reject all invalid IRQ inputs to IRQ control syscall
This updates the proofs for a change in the C code. The IRQ control
syscall now returns an error whenever the IRQ parameter is not a valid
IRQ value. Previously, the syscall threw away some higher-order bits
before checking for IRQ validity.

Incidentally, the C now only uses the name `irq` for variables of type
`irq_t`, and `irq_w` for variables of type `word_t`. This avoids trouble
with c-parser name mangling.
2017-10-05 07:59:02 +11:00