Commit Graph

3927 Commits

Author SHA1 Message Date
Edward Pierzchalski 36a26e23a5 c-parser: handle symbolic names in assembly
Previously the parser rejected symbolic names in assembly specifiers
(the `[foo]` in `[foo]"r"(bar)`). Since the SIMPL semantics ignores the
body content of assembly, and since these specifiers only affect the
meaning of the body, this rejection was overcautious.

Previously, the parser rejected rval `"i"` and `"rK"` specifiers (which
indicate that the expression is to be used in some kind of immediate
mode). Again, this is out of scope for the SIMPL semantics, so we allow
it.
2019-12-19 17:05:10 +11:00
Edward Pierzchalski 794dfb2f94 c-parser: fix register type to match ptr type 2019-12-18 12:04:48 +11:00
Edward Pierzchalski 31b779739e c-parser: add aliases for useful types 2019-12-18 12:04:48 +11:00
Edward Pierzchalski fb9f5d972d asmrefine riscv: allow assembly 2019-12-18 12:04:48 +11:00
Edward Pierzchalski c3b5f2917a asmrefine: fix debug output
Previously, if a graph refine proof failed it would cause the ML block
defining the debug variable to be discarded; this prevented the user
from investigating the debug output. This change splits the ML block to
avoid the issue.
2019-11-29 13:59:50 +11:00
Victor Phan b9c285400d remove diminished (VER-1158)
diminished takes two caps and asserts that one is equal to the other
except that one may have fewer rights. We remove this definition and all
references to it, replacing diminished with equality.
2019-11-16 01:03:36 +11:00
Gerwin Klein 1970ed0ce0 word_lib internal + crefine: remove duplicate lemma 2019-11-15 12:08:22 +11:00
Gerwin Klein c390ba7404 proofs: adjustments for word_lib changes 2019-11-15 12:08:22 +11:00
Gerwin Klein 3bce45dd25 word_lib: avoid shadowing existing lemma 2019-11-15 12:08:20 +11:00
Gerwin Klein 0fc9ab947d word_lib: add new material from l4v to AFP; cleanup 2019-11-15 12:08:20 +11:00
Gerwin Klein 9a1231bf97 word_lib internal: move up lemmas from Word_Lemmas_Internal
(non-AFP part)
2019-11-15 12:08:20 +11:00
Gerwin Klein 13143d7246 word_lib internal: cleanup 2019-11-15 12:08:20 +11:00
Gerwin Klein ad8923293e word_lib: shorter, more automatic proofs 2019-11-15 12:08:20 +11:00
Gerwin Klein e5ce178f1e word_lib: add mask_range 2019-11-15 12:08:20 +11:00
Gerwin Klein 821085f7b1 ainvs: move mask_range into Word_Lib 2019-11-15 12:08:20 +11:00
Gerwin Klein 3cffac8415 word_lib: word_eqI and word_eqI_solve methods
Improvements on initial version by Thomas Sewell
2019-11-15 12:08:20 +11:00
Gerwin Klein 16c15920a8 lib: move word_eqI_solve out of HaskellLemmaBucket 2019-11-15 12:08:20 +11:00
Gerwin Klein 59818de68e lib: avoid ambiguous syntax 2019-11-15 12:04:50 +11:00
Gerwin Klein bdd882d17e lib: more lifting rules for validE_R and validE_E 2019-11-15 12:04:50 +11:00
Gerwin Klein c826b33b88 bisim: Bisim session for ARM, X64, RISCV64
ARM_HYP would be possible, but require arch split for hyp-faults.
2019-11-15 12:04:50 +11:00
Gerwin Klein 55aeefdb64 x64: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Gerwin Klein b820b13d06 riscv: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Victor Phan 9fda73732a x64 crefine: update for seL4 bugfix [GITHUB PR 107]
Always invalidate TLB during unmapPage.
2019-11-14 18:05:24 +11:00
Edward Pierzchalski 831d3b4f70 docs: clarify installation instructions
Miscellaneous changes to make instructions easier to follow, as well as
updating instructions for Haskell Stack (which is no longer available on
Debian Testing).
2019-11-14 16:12:49 +11:00
Victor Phan 1db6ae7cf0 riscv: add kdev_base/kdevBase to handle RISCVVSpaceDeviceWindow and update proofs
- Add HiFive.hs to replace Spike.hs, it's the same except for kdevBase
  addition.
- Originally called KDEV_PPTR in the C Code, to be changed to KDEV_BASE
  across all architectures.
- Add RISCVVSpaceDeviceWindow case for valid_uses_2 definition.
2019-11-13 16:27:30 +11:00
Victor Phan 79513ae604 riscv: update to HiFive platform from Spike
- Increase maxIRQ to 53
- Change keywords to build HiFive instead of Spike
2019-11-13 16:26:55 +11:00
Victor Phan c7fb4dcf2b riscv aspec/ainvs: redefine kernel_elf_base to point to be kernelELFBase 2019-11-13 16:08:52 +11:00
Victor Phan 6f94fff163 riscv aspec/ainvs: rename kernel_base to kernel_elf_base 2019-11-13 16:08:42 +11:00
Edward Pierzchalski 44815388e9 asmrefine: blacklist failing functions
These are boot code functions which are failing SEAR for "interesting"
reasons. For expediency we're skipping them in a very visible way.
2019-11-13 11:40:43 +11:00
Victor Phan f8b7f61445 riscv refine: update and close sorries for adding IRQ invocations
irqInvalid is manually requalified into Interrupt_R. If it's defined for all
architectures, then can be requalified instead in the more suitable
spec/machine/MachineExports.thy

Reimplement the following primrecs:
- arch_irq_control_inv_relation
- arch_irq_control_inv_valid'
- irq_control_inv_valid'

Add the following lemmas:
- arch_check_irq_corres
- crunches arch_check_irq, checkIRQ
- arch_check_irq_valid
- arch_check_irq_valid'
- no_fail_setIRQTrigger
- setIRQTrigger_corres
- dmo_setIRQTrigger_invs'
2019-11-12 18:28:40 +11:00
Victor Phan 67b8237e61 lib: add word lemma
Add of_nat_unat_le_mask_ucast: equality of words where one is wrapped with
of_nat (unat _).
2019-11-12 18:28:40 +11:00
Victor Phan d1f3afc4f2 riscv ainvs: close sorries for adding IRQ invocations
- Add setTrigger lemmas: setIRQTrigger_irq_masks, dmo_setIRQTrigger_invs
  and no_irq_setIRQTrigger
- Modify primrec arch_irq_control_inv_valid_real to include similar
  conditions to its equivalent in ARM, but with the minor chnage of irq !=
  irqInvalid.
2019-11-12 18:28:40 +11:00
Victor Phan 8bf03d45a0 riscv haskell/design: add and implement IRQ invocations
setIRQTrigger added but unimplemented because it's a machine op.
irqInvalid added, set to 0, since this is what's defined on the Spike
platform, may need to implement irqInvalid for other platforms if we
want generality for later proofs (Refine).
check, decode, perform IRQ control fully implemented to match the CSpec.
2019-11-12 18:28:40 +11:00
Victor Phan 55408a48af riscv aspec: implement IRQ check, decode and invoke control functions
These functions were originally doing throwError IllegalOperation or
returnOk (). Now they have been reimplemented to match the CSpec.

In arch_check_irq, an error is thrown if IRQ is greater than maxIRQ or
is equal to irqInvalid. The error that gets returned to the user however
is a RangeError from 1 to maxIRQ.
2019-11-12 18:28:40 +11:00
Victor Phan 3ef1e6845c riscv refine: update after adding thread id registers to TCB 2019-11-12 18:28:40 +11:00
Victor Phan 0d7c2fff48 riscv ainvs: add support to thread id registers 2019-11-12 18:28:40 +11:00
Victor Phan 39d314137e riscv haskell: add support to thread id registers 2019-11-12 18:28:40 +11:00
Victor Phan 79da089c2e riscv aspec: update for moving IPC buffer register to thread-local storage 2019-11-12 18:28:40 +11:00
Victor Phan 26b25838d0 riscv ainvs: close sorry for introducing kernelELFBase 2019-11-12 18:28:40 +11:00
Victor Phan d4f302ae7f riscv haskell: rename kernelBase to kernelELFBase and fix its value 2019-11-12 18:28:40 +11:00
Victor Phan 453233faad riscv aspec: rename kernelBase to kernelELFBase and update address space layout comment 2019-11-12 18:28:40 +11:00
Gerwin Klein 0661581e44 runtests: enable RISCV64 Orphanage test 2019-11-12 18:28:40 +11:00
Victor Phan e4d83b313a riscv refine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-11-12 18:28:40 +11:00
Gerwin Klein a5e27933a5 riscv: cleanup; resolve remaining FIXMEs 2019-11-12 18:28:40 +11:00
Gerwin Klein d2584a3692 cleanup: collect word lemmas 2019-11-12 18:28:40 +11:00
Gerwin Klein cbc31e31e1 ainvs+refine: provide def of mask_range in InvariantsPre
(used to be ptr_range in riscv, which is too overloaded)
2019-11-12 18:28:40 +11:00
Gerwin Klein 82bcbdc137 riscv ainvs: prove that example state satisfies invs 2019-11-12 18:28:40 +11:00
Gerwin Klein 090894c990 riscv aspec+ainvs: define a consistent initial page table
Simpler than the real kernel layout, but will show that invariants are
consistent.
2019-11-12 18:28:39 +11:00
Gerwin Klein 9d81f85c38 riscv: force vptr alignment in PTMap decode
Instead of checking for alignment, mask out the bottom bits to force the
vptr stored in the cap into the correct alignment for the level to be mapped.

See also SELFOUR-2162
2019-11-12 18:28:39 +11:00
Gerwin Klein 12f2d82f86 riscv refine: Orphanage sorry-free 2019-11-12 18:28:39 +11:00