7b9249fe2a
riscv design: port new asserts into design spec
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
fca56f750b
riscv haskell: additional assertions for CRefine
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
6be8b794ec
riscv haskell: sync order with C enum
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
e650f39de3
riscv crefine: update for C setIRQTrigger changes
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Update machine op assumption and remove Arch_invokeIRQControl_ccorres sorry.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
0ee70f00a5
riscv crefine: clear 3 sorries in Invoke_C
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Resolved via C changes.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
461fca472d
riscv crefine: sorried Invoke_C
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Two big ones where crefine machinery leads us astray, and a few small
ones waiting on a spec update on api object enums.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
917ccdf284
riscv crefine: reduce sorries in VSpace_C and Retype_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
8871074809
riscv crefine: another long/demunged name in Machine_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
8659e32058
riscv crefine: Recycle_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
64d049f140
riscv crefine: update IsolatedThreadAction for new setVMRoot assertion
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
877aee385c
riscv crefine: sorried Interrupt_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
2e16aae27f
riscv crefine: Retype_C with sorried copyGlobalMappings
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
04b781a79a
riscv crefine: sorried Delete_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
e9e562c33d
riscv crefine: introduce registers_count type abbrev
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
70ee5750f6
riscv haskell+refine: add assertion to setVMRoot
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The assertion is provable from the abstract invariants, and used in
CRefine to conclude that the test wether the vspace root cap is mapped
can be left out.
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
adf175bc1b
riscv crefine: update for C user exception message change
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
3a71e0d6ad
riscv haskell: update exceptionMessage to conform to C
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Now contains only FaultIP and SP.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
6ca33d54e7
riscv crefine: reduce by one sorry in Finalise_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
a02357e09e
riscv crefine: machine op parameter name changed
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
eeabaff06e
riscv refine: reduce sorries in Finalise_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
cd82381ae2
riscv refine: add irq ~= irqInvalid to valid_cap'
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
5e886c171f
riscv crefine: sorried Ipc_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
85e1fffe83
riscv crefine: IsolatedThreadAction
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
97f292cab9
riscv crefine: sorried Finalise_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
c38fed430f
riscv crefine: IpcCancel_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
67eaeab106
riscv crefine: SyscallArgs_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
040e54c9e6
riscv crefine: StoreWord_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
4e93309925
riscv crefine: reduce warnings in VSpace_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
d3e42da647
riscv crefine: clear 4 sorries in VSpace_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
f275c2c4c1
riscv crefine: clear sorries in Detype_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
61abd075c2
riscv crefine: clear remaining CSpace_C sorry
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
fc4f83a128
riscv crefine: clear CSpace_C sorries up to kernel change
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cap_get_capIsPhysical needs a C code change for its default case.
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
cdd468fa77
riscv crefine: clear sorry in TcbQueue_C
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
c5918e8479
riscv crefine: close sorry in PSpace
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Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
e4ce4f8945
riscv crefine: sorry VSpace_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
3a2bfe5a93
riscv crefine: sync frame PTE rights with C updates
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
7bec00882e
riscv crefine: sorry Detype_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
df89db9550
riscv crefine: sorry TcbQueue_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
9c5b7fbff6
riscv crefine: sorry PSpace_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
0d582877a1
riscv crefine: StateRelation_C: adjust register_from_H
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
bc7b66e788
riscv crefine: TcbAcc_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
9a86c195ed
riscv crefine: add valid_untyped' to ArchMove_C
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Opted to use old form of statement and adjust proof, as CRefine proofs
are not aware of mask_range and a cleanup of that sort would take too
long at this time.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
533dd333ac
riscv crefine: more ArchMove_C lemmas from X64
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
6fc6aeb20c
riscv cspec/crefine: update ctcb_size_bits to 9
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One bit smaller than X64. Removes FIXME.
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
e93a475bd6
riscv refine: update for tcbBlockSizeBits == 10
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
84fd22524b
design/haskell spec: arch split for tcbBlockSizeBits
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`tcbBlockSizeBits` was previously defined to be `wordSizeCase 9 11`
universally, but this claim does not hold anymore since it takes the
value 10 on RISCV64. Therefore an arch split for `tcbBlockSizeBits` and
affected definitions are made. The constant and its definition needs to
be requalified so that proofs in Refine can access it through the
constant objBits_defs.
Signed-off-by: Victor Phan <Victor.Phan@data61.csiro.au>
2020-06-08 20:41:09 +08:00
cc367d61b2
riscv aspec+ainvs: update tcb bits to 10
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
df2c0c30c1
riscv crefine: CSpace_All
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
dd0d36fbe1
riscv crefine: sorry CSpace_RAB_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
11d988137b
riscv crefine: sorried CSpace_C
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Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein
Rafal Kolanski