| .. |
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ArchAcc_R.thy
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riscv refine: more guard cross-over rules
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2019-11-12 18:28:39 +11:00 |
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Bits_R.thy
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riscv refine: add ArchFrameCap to capSimps and friends
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2019-11-12 18:28:39 +11:00 |
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CSpace1_R.thy
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riscv refine: set up CSpace1_R (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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CSpace_I.thy
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riscv refine: set up CSpace_I (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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CSpace_R.thy
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riscv refine: set up CSpace_R (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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Corres.thy
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riscv refine: set up Bits_R, Corres, EmptyFail
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2019-11-12 18:28:38 +11:00 |
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Detype_R.thy
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riscv refine: add valid_arch_cap' to invariants
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2019-11-12 18:28:39 +11:00 |
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EmptyFail.thy
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riscv refine: set up Bits_R, Corres, EmptyFail
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2019-11-12 18:28:38 +11:00 |
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EmptyFail_H.thy
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riscv refine: initial skeleton
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2019-11-12 18:28:38 +11:00 |
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Include.thy
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riscv refine: initial skeleton
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2019-11-12 18:28:38 +11:00 |
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InterruptAcc_R.thy
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riscv refine: set up InterruptAcc_R
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2019-11-12 18:28:39 +11:00 |
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Invariants_H.thy
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riscv refine: add valid_arch_cap' to invariants
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2019-11-12 18:28:39 +11:00 |
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Invocations_R.thy
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riscv refine: add Invocations_R
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2019-11-12 18:28:39 +11:00 |
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IpcCancel_R.thy
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riscv refine: set up IpcCancel (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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KHeap_R.thy
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riscv refine: close sorry in KHeap_R
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2019-11-12 18:28:39 +11:00 |
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LevityCatch.thy
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riscv refine: initial skeleton
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2019-11-12 18:28:38 +11:00 |
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Machine_R.thy
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riscv refine: initial skeleton
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2019-11-12 18:28:38 +11:00 |
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RAB_FN.thy
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riscv refine: fill in RAB_FN.thy
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2019-11-12 18:28:39 +11:00 |
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Refine.thy
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riscv refine: initial skeleton
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2019-11-12 18:28:38 +11:00 |
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Retype_R.thy
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riscv refine: add valid_arch_cap' to invariants
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2019-11-12 18:28:39 +11:00 |
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Schedule_R.thy
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riscv refine: set up Schedule_R (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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StateRelation.thy
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riscv refine: add ArchFrameCap to capSimps and friends
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2019-11-12 18:28:39 +11:00 |
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SubMonad_R.thy
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riscv refine: set up KHeap_R (1 sorry) and SubMonad_R
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2019-11-12 18:28:38 +11:00 |
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TcbAcc_R.thy
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riscv refine: weaken precondition of threadSet_invs_trivialT
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2019-11-12 18:28:39 +11:00 |
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Untyped_R.thy
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riscv refine: set up Untyped_R (0 sorries)
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2019-11-12 18:28:39 +11:00 |
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VSpace_R.thy
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riscv refine: simplify setASIDPool_invs
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2019-11-12 18:28:39 +11:00 |
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