85 lines
3.3 KiB
C
85 lines
3.3 KiB
C
/*
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* Copyright 2014, General Dynamics C4 Systems
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#include <stdint.h>
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/* Memory map for GIC distributor */
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typedef struct gic_dist_map_t {
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uint32_t enable; /* 0x000 */
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uint32_t ic_type; /* 0x004 */
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uint32_t dist_ident; /* 0x008 */
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uint32_t res1[29]; /* [0x00C, 0x080) */
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uint32_t security[32]; /* [0x080, 0x100) */
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uint32_t enable_set[32]; /* [0x100, 0x180) */
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uint32_t enable_clr[32]; /* [0x180, 0x200) */
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uint32_t pending_set[32]; /* [0x200, 0x280) */
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uint32_t pending_clr[32]; /* [0x280, 0x300) */
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uint32_t active[32]; /* [0x300, 0x380) */
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uint32_t res2[32]; /* [0x380, 0x400) */
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uint32_t priority[255]; /* [0x400, 0x7FC) */
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uint32_t res3; /* 0x7FC */
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uint32_t targets[255]; /* [0x800, 0xBFC) */
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uint32_t res4; /* 0xBFC */
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uint32_t config[64]; /* [0xC00, 0xD00) */
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uint32_t spi[32]; /* [0xD00, 0xD80) */
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uint32_t res5[20]; /* [0xD80, 0xDD0) */
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uint32_t res6; /* 0xDD0 */
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uint32_t legacy_int; /* 0xDD4 */
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uint32_t res7[2]; /* [0xDD8, 0xDE0) */
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uint32_t match_d; /* 0xDE0 */
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uint32_t enable_d; /* 0xDE4 */
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uint32_t res8[70]; /* [0xDE8, 0xF00) */
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uint32_t sgi_control; /* 0xF00 */
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uint32_t res9[3]; /* [0xF04, 0xF10) */
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uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
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uint32_t res10[40]; /* [0xF20, 0xFC0) */
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uint32_t periph_id[12]; /* [0xFC0, 0xFF0) */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
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} gic_dist_map;
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/* Memory map for GIC cpu interface */
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typedef struct gic_cpu_iface_map {
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uint32_t icontrol; /* 0x000 */
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uint32_t pri_msk_c; /* 0x004 */
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uint32_t pb_c; /* 0x008 */
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uint32_t int_ack; /* 0x00C */
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uint32_t eoi; /* 0x010 */
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uint32_t run_priority; /* 0x014 */
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uint32_t hi_pend; /* 0x018 */
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uint32_t ns_alias_bp_c; /* 0x01C */
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uint32_t ns_alias_ack; /* 0x020 GIC400 only */
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uint32_t ns_alias_eoi; /* 0x024 GIC400 only */
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uint32_t ns_alias_hi_pend; /* 0x028 GIC400 only */
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uint32_t res1[5]; /* [0x02C, 0x040) */
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uint32_t integ_en_c; /* 0x040 PL390 only */
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uint32_t interrupt_out; /* 0x044 PL390 only */
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uint32_t res2[2]; /* [0x048, 0x050) */
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uint32_t match_c; /* 0x050 PL390 only */
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uint32_t enable_c; /* 0x054 PL390 only */
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uint32_t res3[30]; /* [0x058, 0x0FC) */
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uint32_t active_priority[4]; /* [0x0D0, 0xDC] GIC400 only */
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uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
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uint32_t res4[3];
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uint32_t cpu_if_ident; /* 0x0FC */
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uint32_t res5[948]; /* [0x100. 0xFC0) */
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uint32_t periph_id[8]; /* [0xFC0, 9xFF0) PL390 only */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] PL390 only */
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} gic_cpu_iface_map;
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