86 lines
3.2 KiB
Plaintext
86 lines
3.2 KiB
Plaintext
(*****************************************************************************
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* Copyright (c) 2005-2010 ETH Zurich, Switzerland
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* 2008-2015 Achim D. Brucker, Germany
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* 2009-2016 Université Paris-Sud, France
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* 2015-2016 The University of Sheffield, UK
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************)
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subsection{* Integer Addresses with Ports *}
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theory
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IntegerPort
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imports
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NetworkCore
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begin
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text{*
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A theory describing addresses which are modelled as a pair of Integers - the first being the
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host address, the second the port number.
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*}
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type_synonym
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address = int
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type_synonym
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port = int
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type_synonym
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adr\<^sub>i\<^sub>p = "address \<times> port"
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overloading src_port_int \<equiv> "src_port :: ('\<alpha>::adr,'\<beta>) packet \<Rightarrow> '\<gamma>::port"
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begin
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definition
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"src_port_int (x::(adr\<^sub>i\<^sub>p,'\<beta>) packet) \<equiv> (snd o fst o snd) x"
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end
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overloading dest_port_int \<equiv> "dest_port :: ('\<alpha>::adr,'\<beta>) packet \<Rightarrow> '\<gamma>::port"
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begin
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definition
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"dest_port_int (x::(adr\<^sub>i\<^sub>p,'\<beta>) packet) \<equiv> (snd o fst o snd o snd) x"
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end
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overloading subnet_of_int \<equiv> "subnet_of :: '\<alpha>::adr \<Rightarrow> '\<alpha> net"
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begin
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definition
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"subnet_of_int (x::(adr\<^sub>i\<^sub>p)) \<equiv> {{(a,b::int). a = fst x}}"
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end
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lemma src_port: "src_port (a,x::adr\<^sub>i\<^sub>p,d,e) = snd x"
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by (simp add: src_port_int_def in_subnet)
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lemma dest_port: "dest_port (a,d,x::adr\<^sub>i\<^sub>p,e) = snd x"
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by (simp add: dest_port_int_def in_subnet)
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lemmas adr\<^sub>i\<^sub>pLemmas = src_port dest_port src_port_int_def dest_port_int_def
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end
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