Commit Graph

45 Commits

Author SHA1 Message Date
Corey Lewis 8ffdb5eb76 proof: change simple corres_splitEE cases
perl -0777 -pi -e 's/corres_splitEE *\[ *OF +_ +([^_]\w+) +(\w+)/corres_splitEE[OF \1 _ \2/g' **/*.thy
perl -0777 -pi -e 's/corres_splitEE *\[ *OF +_ +(?!_)/corres_splitEE[OF /g' **/*.thy
perl -0777 -pi -e 's/corres_splitEE *\[ *OF +([^_]\w+) +([^_]\w+)/corres_splitEE[OF \2 \1/g' **/*.thy
perl -0777 -pi -e 's/corres_splitEE *(.*)\)\n\s*prefer +2/corres_splitEE\1\)/g' **/*.thy

Signed-off-by: Corey Lewis <corey.lewis@proofcraft.systems>
2022-10-20 08:59:52 +11:00
Corey Lewis f4e9295424 proof: change simple corres_split_deprecated cases
perl -0777 -pi -e 's/corres_split_deprecated *\[ *OF +_ +([^_].*)\)\n\s*prefer 2/corres_split[OF \1\)/g' **/*.thy
perl -0777 -pi -e 's/corres_split_deprecated *\[ *OF +_ +(?!_)/corres_split[OF /g' **/*.thy
perl -0777 -pi -e 's/corres_split_deprecated *\[ *OF +([^_]\w+) +([^_]\w+) +(.*)\)\n\s*prefer +2/corres_split[OF \2 \1 \3\)/g' **/*.thy
perl -0777 -pi -e 's/corres_split_deprecated *\[ *OF +([^_]\w+) +([^_]\w+)/corres_split[OF \2 \1/g' **/*.thy
perl -0777 -pi -e 's/corres_split_deprecated *(.*)\)\n\s*prefer +2/corres_split\1\)/g' **/*.thy

Signed-off-by: Corey Lewis <corey.lewis@proofcraft.systems>
2022-10-20 08:59:52 +11:00
Gerwin Klein b29a3433ef isabelle2021-1: remove no_take_bit
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2022-03-29 08:38:25 +11:00
Gerwin Klein 43e558cd9b isabelle-2021 arm : update Refine
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-09-30 16:53:17 +10:00
Florian Haftmann d61cffcf61 isabelle-2021: adjusted to new naming convention
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2021-09-30 16:53:17 +10:00
Florian Haftmann ea9a25950d isabelle-2021: ad-hoc adjustions to preview
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2021-09-30 16:53:17 +10:00
Miki Tanaka d054484474 arm refine: define valid_idle' directly, without using itcb
- introduces idle_tcb' defined using tcb fields
- backport from MCS

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Mitchell Buckley 7180ee4e70 refine: Standardise names of some corres lemmas
Ideally all corres lemmas of the form
`corres rrel P P' my_abstract_function myHaskellFunction`
should be named `myHaskellFunction_corres`.

This commit renames over 200 lemmas to match this style.

Signed-off-by: Mitchell Buckley <mitchell.alan.buckley@gmail.com>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
2021-06-21 10:30:04 +10:00
Corey Lewis dd07ffd197 refine: move invariant field update lemmas
Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-03-11 10:42:49 +11:00
Corey Lewis 008969fc02 lib proof: reorder the assumptions of corres_split
Currently this just modifies the rule but not any of the proofs that use
it. The old version is kept for now but should be removed once all of
the proofs are updated.

Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-02-19 11:37:12 +11:00
Gerwin Klein 66b2774155 arm refine: Isabelle2020 update
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Miki Tanaka 0359fb1da0 arm refine: remove interrupt/irq from p_monad
- fix ARM refine proofs for the above change
- use dc instead of intr

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2020-10-25 13:15:00 +11:00
Gerwin Klein c3f3656942 refine + crefine: proof updates for haskell datatype selectors
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-09 10:06:31 +08:00
Gerwin Klein e7f6e97c6b cleanup: remove stray diagnostic commands and comments
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 71e7f87614 haskell/refine/crefine: rename isBlocked to isStopped
sync with corresponding change in C

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-05-06 15:49:02 +10:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Victor Phan f2d1f5ada7 refine/crefine: convert crunch with multiple constants into crunches 2020-02-03 16:29:19 +11:00
Victor Phan 285c47f622 cleanup for crunch_ignore in refine and crefine for all arches
Several constants are are added to the top level crunch_ignore statement in
Bits_R.thy, then removed from individual crunch statements across Refine and
CRefine.
2020-02-03 16:29:18 +11:00
Gerwin Klein 54f557f2b2 refine: invocation label proof updates 2020-02-03 12:56:19 +08:00
Corey Lewis dd48e0d899 proof: update for wp changes
Updated 'wp_once' to 'wp (once)' and removed several stray uses of 'wp_trace'.
2019-10-14 17:12:18 +11:00
MiladKetabi d934d25269 proof update for SELFOUR-1187: seL4 setPriority should attempt a direct schedule
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.
2019-10-06 18:31:19 +11:00
Amirreza Zarrabi 4f93ebe608 refine, crefine: update after adding thread id registers to TCB for SELFOUR-1524 2019-06-28 11:48:24 +10:00
Michael McInerney 0025f29417 refine: update for Isabelle2019 2019-06-13 16:22:33 +10:00
Michael McInerney 4463e9750e SELFOUR-1198: update proofs for correct restart PC
Fixes a case where a thread can go from Running->Inactive->Restart and
use a restart PC that is out of date. An out of date restart PC occurs
when a thread was transitioned to running after being in a blocked
state, but was never scheduled and so did not execute the traps code
that updates the restart PC.

This also renames relevant register names for consistency across
architectures (FaultIP and NextIP).
2019-06-13 11:43:50 +10:00
Edward Pierzchalski 2035f444a0 refine: Remove unused lemmas. 2019-05-28 10:00:10 +10:00
Victor Phan d707c97df9 arm refine: update for new definition of set_object 2019-04-18 14:32:08 +10:00
Rafal Kolanski c02d0406f5 arm refine: update for GrantReply (SELFOUR-6)
Initial setup and sorrying by Thibaut Perami.
2018-12-10 20:01:37 +11:00
Gerwin Klein 6b9d9d24dd Isabelle2018: new "op x" syntax; now is "(x)"
(result of "isabelle update_op -m <dir>")
2018-08-20 09:06:35 +10:00
Maksym Bortin 9d315cda20 ainvs+refine: update proofs for SetTLSBase (VER-807) 2018-07-03 13:42:19 +10:00
Corey Lewis 2d0baab462 Proof update for crunch changes 2018-04-04 14:13:55 +10:00
Thomas Sewell 0f38e20094 Many proof repairs. 2018-03-16 14:57:51 +11:00
Thomas Sewell 652cbb966e Initial proof updates for combinator changes. 2018-03-16 14:53:22 +11:00
Gerwin Klein 2d9de5b9a6 ARM refine: proof update for user_context refactor 2018-03-08 18:41:28 +11:00
Michael Sproul f0795805d1 SELFOUR-1016: fix confused deputy problem when setting priorities 2018-02-26 11:19:43 +11:00
Michael Sproul 995b88cefa SELFOUR-707: schedule highest priority thread on setPriority 2018-01-19 16:08:11 +11:00
Joel Beeren a5a5edc832 VER-849: abstractly declare a threads registers have changed
This removes an ifdef present in invokeTCB_(Copy|Write)Registers, and
adds the function Arch_postModifyRegisters which does nothing on any
arch except x86-64.
2017-12-13 12:13:36 +11:00
Rafal Kolanski 3a22487cf3 arm: revise scheduler / fastpath / scheduler bitmaps (SELFOUR-242)
Colloquially known as "invert-fastpath".

Update verification efforts on ARM for the following seL4 changes:
- scheduling decisions done in possibleSwitchTo are moved to the
  scheduler
  - possibleSwitchTo only checks whether the candidate is valid for a
    fast switch, not its priority, accepting possible candidates
    immmediately as a switch-to scheduler action
  - the scheduler checks the candidate against the current thread and
    against the bitmaps before making a decision
  - attemptSwitchTo and switchIfRequiredTo are gone
  - scheduler is now more complicated, and numerous proofs related to it
    are rewritten from scratch
- fast path now checks ready queues via the scheduler bitmaps
- L2 scheduler bitmap order reversed for better cache locality

Many iterations between the kernel and verification teams were needed
to get this right.
2017-11-27 22:05:34 +11:00
Matthew Brecknell 48b3a8b4ca update object and field widths for x64, and remove some magic numbers
In X64 update the following to match the C kernel:
  - TCB size-bits (11).
  - Endpoint size-bits (4).
  - Guard bits (58).
  - Message registers.

For all architectures, replace magic numbers with defined constants in
specifications, and as far as possible in proofs:
  - tcb_bits in abstract spec.
  - tcbBlockSizeBits, cteSizeBits, ntfnSizeBits, epSizeBits in Haskell
    spec, Haskell and C refinement proofs.
2017-10-26 14:05:35 +11:00
Joel Beeren 42401684b0 refine: integrate all architectures 2017-08-09 17:02:49 +10:00
Alejandro Gomez-Londono 796887d9b1 Removes all trailing whitespaces 2017-07-12 15:13:51 +10:00
Miki Tanaka 41fe1a0845 update proofs for SELFOUR-30/291 "Reschedule on self-modification"
- SELFOUR-30 Reschedule when changing own IPC buffer
Previously if you invoked the TCB of the current thread and
changed the IPC buffer frame this would not immediately take
affect, as the kernels view of the current IPC buffer is
updated in Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.

- SELFOUR-291 Reschedule when changing own registers
Previously if you wrote to TCB of the current thread and
changed the TLS_BASE this would not immediately take
affect, as the kernel only updates this register in
Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.
2017-06-26 15:52:35 +10:00
Pang Luo da28d94974 VER-717: refactor tpidrurwRegister and fix corresponding proof 2017-05-05 15:17:41 +10:00
Joel Beeren 71e2db88a4 arm: refactor sanitise_register to take a bool instead of a kernel_object
This simplified the sanitise_register logic in CRefine for arm-hyp.
2017-05-03 21:51:57 +10:00
Gerwin Klein 520921351a provide TCB argument for sanitiseRegister
Other platforms such as arm-hyp will need to look into additional TCB state
such as VCPU in sanitiseRegister. This commit provides the scaffolding for
that.
2017-02-12 12:54:42 +11:00
Rafal Kolanski 7657681fca move refine/* to refine/ARM/*, parametrise over $L4V_ARCH 2017-01-30 12:22:22 +11:00