Commit Graph

147 Commits

Author SHA1 Message Date
Matthew Brecknell b77f83c57b riscv: rename sbadaddr -> stval
Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2020-08-26 15:24:06 +10:00
Rafal Kolanski c160f4053d riscv machine: add alternative definition for pptrUserTop
(presents numeral directly without further unfolding)

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Victor Phan 461a798412 aspec: arch split on invokeIRQHandler
The RISCV implementation of invokeIRQHandler calls plic_complete_claim
instead of maskInterrupt. plicCompleteClaim is added as a machine op
and invokeIRQHandler has been arch split for the ACKIrq case.

Signed-off-by: Victor Phan <Victor.Phan@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Victor Phan 190d3b402a riscv spec/ainvs: update IRQs to target hifive platform
- Increase IRQ word size from 3 to 6 to match IRQ_CNODE_SLOT_BITS in
  sel4 config.
- Bump maxIRQ up to 54.
- Fix broken inequality proof by changing constant that depended on IRQ
  word size.
2020-03-27 15:50:46 +11:00
Gerwin Klein c68915b92b license: provide documentation under CC-BY-SA-4.0
Datat61 provides all docs under CC-BY-SA-4.0.
2020-03-16 14:19:15 +08:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Gerwin Klein 8d12d8e4be licenses: tag .md and document file 2020-03-02 18:52:15 +08:00
Rafal Kolanski f9ea44ef89 arm-hyp: update spec+proofs for multi-VM support
Highlights:
- new reserved IRQ and associated handler: VPPIEvent
- VPPI events are virtual interrupts we can forward to VMs; currently there is
  only one event: virtual timer interrupt
- VGICMaintenance and VPPIEvent can both receive late interrupts from hardware,
  which are now discarded instead of being delivered to current thread
- given only one possible VPPI event, simplifier tends to mop up more than it
  should, making some proofs fragile w.r.t. adding a new VPPI event
- the order of some lemmas/specs needed shuffling, as now VCPU code needs some
  interrupt code, which uses VCPU code
2020-02-19 10:52:07 +11:00
Victor Phan 1db6ae7cf0 riscv: add kdev_base/kdevBase to handle RISCVVSpaceDeviceWindow and update proofs
- Add HiFive.hs to replace Spike.hs, it's the same except for kdevBase
  addition.
- Originally called KDEV_PPTR in the C Code, to be changed to KDEV_BASE
  across all architectures.
- Add RISCVVSpaceDeviceWindow case for valid_uses_2 definition.
2019-11-13 16:27:30 +11:00
Victor Phan 79513ae604 riscv: update to HiFive platform from Spike
- Increase maxIRQ to 53
- Change keywords to build HiFive instead of Spike
2019-11-13 16:26:55 +11:00
Victor Phan 55408a48af riscv aspec: implement IRQ check, decode and invoke control functions
These functions were originally doing throwError IllegalOperation or
returnOk (). Now they have been reimplemented to match the CSpec.

In arch_check_irq, an error is thrown if IRQ is greater than maxIRQ or
is equal to irqInvalid. The error that gets returned to the user however
is a RangeError from 1 to maxIRQ.
2019-11-12 18:28:40 +11:00
Victor Phan 453233faad riscv aspec: rename kernelBase to kernelELFBase and update address space layout comment 2019-11-12 18:28:40 +11:00
Gerwin Klein 8ab9888cf4 riscv aspec: set irq type to lowest word length that fits maxIRQ
The irq type determines the size of the IRQ CNode in the abstract spec, which
(in C) is the smallest power of two that fits maxIRQ.
2019-11-12 18:28:39 +11:00
Rafal Kolanski 89aafed912 riscv aspec+ainvs+haskell: update kernelBase, paddrLoad to match C
update for changeset 897aaf5b13f39ba2b9ca8ade3a58d1350eb42ad7

This changes properties of kernel_base, thereby invalidating two unused
lemmas: mask_out_8_le_kernel_base, mask_out_8_less_kernel_base
2019-07-31 16:55:32 +10:00
Gerwin Klein 23866cbae9 riscv platform: sync seL4_UserTop with C
now in sync with master@63ed19c9b7d972eb4af73c666484e277b0d4cf83
2019-07-31 16:55:31 +10:00
Gerwin Klein ac9ff925ce riscv platform: removed unused region in address space diagram
co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2019-07-31 14:13:56 +10:00
Amirreza Zarrabi 0116126a3c design: add support to thread id registers 2019-06-28 11:20:22 +10:00
Gerwin Klein c34840d09b global: isabelle update_cartouches 2019-06-14 11:41:21 +10:00
Michael McInerney 4463e9750e SELFOUR-1198: update proofs for correct restart PC
Fixes a case where a thread can go from Running->Inactive->Restart and
use a restart PC that is out of date. An out of date restart PC occurs
when a thread was transitioned to running after being in a blocked
state, but was never scheduled and so did not execute the traps code
that updates the restart PC.

This also renames relevant register names for consistency across
architectures (FaultIP and NextIP).
2019-06-13 11:43:50 +10:00
Gerwin Klein 558aa5ca05 riscv platform: address space layout diagram; fixed pAddr_base 2018-11-06 14:14:26 +11:00
Mitchell Buckley 8173a37c2d Updated specs and proofs for SELFOUR-1491: control IRQ triggering on ARM. 2018-09-19 16:18:09 +10:00
Gerwin Klein 1597395f03 riscv aspec: style + docs 2018-09-07 08:13:13 +10:00
Gerwin Klein 395a1eede5 riscv machine: update copyright headers for RISCV64 work 2018-09-07 08:13:13 +10:00
Gerwin Klein 01307aeeb0 riscv machine: define setVSpaceRoot, update read_sbadaddr 2018-09-07 08:13:13 +10:00
Gerwin Klein 84110bd84a Isabelle2018 riscv: ExecSpec 2018-08-20 09:06:37 +10:00
Gerwin Klein 6b9d9d24dd Isabelle2018: new "op x" syntax; now is "(x)"
(result of "isabelle update_op -m <dir>")
2018-08-20 09:06:35 +10:00
Gerwin Klein 011e08458e Isabelle2018: new comment syntax
(result of "isabelle update_comments <dirs>")
2018-08-20 09:06:35 +10:00
Gerwin Klein b5cdf4703f globally use session-qualified imports; add Lib session
Session-qualified imports will be required for Isabelle2018 and help clarify
the structure of sessions in the build tree.

This commit mainly adds a new set of sessions for lib/, including a Lib
session that includes most theories in lib/ and a few separate sessions for
parts that have dependencies beyond CParser or are separate AFP sessions.
The group "lib" collects all lib/ sessions.

As a consequence, other theories should use lib/ theories by session name,
not by path, which in turns means spec and proof sessions should also refer
to each other by session name, not path, to avoid duplicate theory errors in
theory merges later.
2018-08-20 09:06:34 +10:00
Gerwin Klein 9a4d2677e3 lib+spec: move definition of machine_word to Word_Lib
JIRA VER-963
2018-08-06 11:22:52 +10:00
Gerwin Klein 0ca5f831a1 x64 machine: cleanup 2018-08-06 11:18:41 +10:00
Michael Sproul b91ee8e4d0 x64: spec+ainvs+refine: add machine ops for nativeThreadUsingFPU and switchFpuOwner 2018-07-05 16:23:15 +10:00
Michael Sproul 0b978bae61 x64: spec: changes for IRQ invocations (VER-879) 2018-07-05 16:23:15 +10:00
Matthew Brecknell f649240cde x64: CR3 and machine op updates for Meltdown 2018-07-05 16:23:15 +10:00
Gerwin Klein 8744fb20d7 x64 abstract/machine: introduce and use FPUNullState
The FPU state is opaque, and its null state is not necessary an array of zeroes.
Instead, the null state is a snapshot taken after initialisation.
2018-07-05 16:23:15 +10:00
Corey Lewis 2b8a2ebfbe spec: add SetTLSBase invocation and update the registers (VER-807) 2018-07-03 13:42:17 +10:00
Gerwin Klein a84b7c624e riscv machine: style 2018-06-27 10:06:48 +02:00
Gerwin Klein aa510dbb93 riscv machine: add remaining machine interface
These are unused in RISCV64 at the moment, but referred to
in generic code, and will likely need to be filled in for
real hardware later.
2018-06-27 10:06:48 +02:00
Rafal Kolanski 115a9ad266 riscv machine: define pptrUserTop and pageColourBits 2018-06-27 10:06:47 +02:00
Rafal Kolanski 39b8b1cb28 riscv design: sFence and readSBADAddr -> sfence and read_sbadaddr 2018-06-27 10:06:47 +02:00
Rafal Kolanski ce937c5797 riscv design: update ptrFromPAddr/addrFromPPtr to match C 2018-06-27 10:06:47 +02:00
Gerwin Klein 8e4f85c7d5 riscv spec/machine: adjust defs for RISCV64 2018-06-27 10:06:47 +02:00
Gerwin Klein 05925b889d riscv design: initial RISCV64 setup 2018-06-27 10:06:47 +02:00
Rafal Kolanski 15d6b62040 arm: address setCurrentPD mismatch between abstract/haskell/C
ARM setCurrentPD was recently refactored as part of multi-VM support for
ARM_HYP. The Haskell was updated correctly, and the C was not.
Unfortunately, setCurrentPD was manually redefined in MachineOps.thy for
ARM hiding the change, making the C look correct when it wasn't.

We scrap the second definition of setCurrentPD, load it from the Haskell,
and have an abstract set_current_pd that's a bit simpler to refine down
from.

The proofs are updated for the above change and the update to the C
setCurrentPD that was breaking on KZM.
2018-06-22 11:59:30 +10:00
Rafal Kolanski 4a3d7a958c arm-hyp: update proofs for SELFOUR-584: running multiple VMs on ARM
As requested by verification, hypervisor registers are now an
enumeration-indexed array rather than individual fields. This cleans up
some of the proof. Additionally, we sweep some non-complexity under the
machine op rug: vcpu_hw_write/read_reg_ccorres is as deep as we go,
rather than specifying every operation and proving that
vcpu_hw_write seL4_VCPUReg_REG calls set_REG for every REG

I took this opportunity to clean up some arm-hyp definitions and proofs,
so some whitespace cleanup got tangled in.
2018-06-15 18:48:47 +10:00
Gerwin Klein d9c08fc73f aspec/haskell/machine: refactor user_context interface
- remove separate abstract set_/get_register implementation, directly use machine op
 - make interface aware that user_context does not always need to equal
   (register => machine_word)
 - introduce FPU state on x64
2018-03-08 18:41:28 +11:00
Joel Beeren 0c9d7269d4 x64: miscellaneous constant updates (VER-845, VER-852)
Updated syscallMessage register list, maxIRQ to match C code
2017-12-13 12:13:36 +11:00
Matthew Brecknell 8c549b6764 x64: remove all trailing whitespace 2017-08-11 14:19:39 +10:00
Matthew Brecknell f4a220e587 x64: remove generated exec spec 2017-08-09 17:02:49 +10:00
Matthew Brecknell 22999e54a3 aspec: integrate all architectures 2017-08-09 16:57:30 +10:00
Matthew Brecknell 238e8b307e x64: merge master 2017-07-21 11:27:12 +10:00