Commit Graph

747 Commits

Author SHA1 Message Date
Rafal Kolanski 860a26880f isabelle-2021: x64 refine update
Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2021-09-30 16:53:17 +10:00
Rafal Kolanski fb93de1444 isabelle-2021: arm-hyp refine update
Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2021-09-30 16:53:17 +10:00
Gerwin Klein 43e558cd9b isabelle-2021 arm : update Refine
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-09-30 16:53:17 +10:00
Florian Haftmann d61cffcf61 isabelle-2021: adjusted to new naming convention
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2021-09-30 16:53:17 +10:00
Florian Haftmann ea9a25950d isabelle-2021: ad-hoc adjustions to preview
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2021-09-30 16:53:17 +10:00
Gerwin Klein 81b95eb6bf READMEs: fix publication links
PDFs and abstracts have moved to trustworthy.systems/

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-25 11:22:05 +10:00
Miki Tanaka 7648bf01e1 arm/arm_hyp/x64/riscv refine: add a method for setter valid_idle' rules
- in VSpace_R
- the same method added to each arch; would be good to unify via
  arch split in the future
- also includes some style cleanup

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Miki Tanaka 09434ab8ff x64 refine: define valid_idle' directly, without using itcb
Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Miki Tanaka 4da06d81ad armhyp refine: define valid_idle' directly, without using itcb
- this introduces idle_tcb' which is defined directly using tcb fields
- backport from MCS ARM Refine

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Miki Tanaka d054484474 arm refine: define valid_idle' directly, without using itcb
- introduces idle_tcb' defined using tcb fields
- backport from MCS

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Miki Tanaka de7c2f7605 riscv refine: define valid_idle' directly, without using itcb
- this introduces idle_tcb' which is defined directly using tcb fields
- backport from MCS ARM Refine

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Miki Tanaka 4ecf7755f3 arm refine: remove magic numbers from valid_irq_node' and global_refs'
Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2021-07-24 12:09:57 +10:00
Ryan Barry 0d53d6909f lib+ainvs+access+refine: resolve most of the new fixmes
Signed-off-by: Ryan Barry <ryan.barry@unsw.edu.au>
2021-07-22 10:44:43 +10:00
Mitchell Buckley 2cf89e20c8 Cleanup some FIXMEs in AInvs and related sessions
Mostly moving lemmas up into various lemma bucket theories. Also:
* replace cte_wp_at_eqD with cte_wp_at_norm (equal lemmas)
* pd_shifting_gen generalise pd_shifting' in 2 architectures
* remove some redundant crunch lemmas

Signed-off-by: Mitchell Buckley <Mitchell.Buckley@data61.csiro.au>
2021-07-16 14:13:07 +10:00
Mitchell Buckley 184bdfb954 refine: fix regression caused by bad theory import
Importing Init_R into ADT_H was causing EmptyFail_H to fail. Since
no other theories actually depend on Init_R we can instead include
it in the Refine session directly.

Signed-off-by: Mitchell Buckley <mitchell.alan.buckley@gmail.com>
2021-06-27 10:13:01 +10:00
Mitchell Buckley ee3b84fb57 refine: Give a trivial member of the abstract-haskell state relation
Describe an extremely simple abstract kernel state, and haskell state
that obey the state relation. These states are `zeroed` in the sense
that they have empty heaps, and default values of 0, False, None, []
and similar in all fields.

These states do not satisfy invs or invs', and this is not as strong
a result as showing that kernel initial states satisfy the state
relation, but it is a good sanity check on the relation itself.

Signed-off-by: Mitchell Buckley <mitchell.buckley@data61.csiro.au>
2021-06-26 10:58:14 +10:00
Matthew Brecknell fd01872121 always use `addrFromKPPtr` for kernel addresses
This verifies a C kernel patch (seL4/seL4#409) which consolidates
translation between virtual and physical addresses, and makes it
consistent across architectures. In particular, we always use
`addrFromKPPtr`, even on architectures that don't use a distinct region
to map the kernel ELF. This will facilitate future improvements which
move the ELF mapping into a distinct virtual address region.

Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2021-06-25 16:31:22 +10:00
Mitchell Buckley 7180ee4e70 refine: Standardise names of some corres lemmas
Ideally all corres lemmas of the form
`corres rrel P P' my_abstract_function myHaskellFunction`
should be named `myHaskellFunction_corres`.

This commit renames over 200 lemmas to match this style.

Signed-off-by: Mitchell Buckley <mitchell.alan.buckley@gmail.com>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
2021-06-21 10:30:04 +10:00
Corey Lewis dd07ffd197 refine: move invariant field update lemmas
Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-03-11 10:42:49 +11:00
Corey Lewis 5323aad95a refine: remove duplicated lemmas
Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-03-11 10:42:49 +11:00
Gerwin Klein bf5b97500a trivial: fix links to papers
The TS website has settled on no `.pml` postfix

Signed-off-by: Gerwin Klein <kleing@unsw.edu.au>
2021-03-02 11:44:22 +11:00
Corey Lewis 008969fc02 lib proof: reorder the assumptions of corres_split
Currently this just modifies the rule but not any of the proofs that use
it. The old version is kept for now but should be removed once all of
the proofs are updated.

Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2021-02-19 11:37:12 +11:00
Gerwin Klein ba38ae33ab update publications links
The links to nicta.com.au have stopped working, so the publication links
now point to the TS publication pages.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-11-23 17:06:46 +11:00
Rafal Kolanski 6a587f7c20 x64: update for platform constant changes
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-11-16 16:52:40 +11:00
Rafal Kolanski 0df39b8ed5 riscv: update for platform constant changes
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-11-16 16:52:40 +11:00
Rafal Kolanski 9ed45e17bd arm+arm-hyp: kernelBase and physMappingOffset renames
This brings the naming convention closer to the other architectures,
closer to the Haskell, and closer to the constant renames that happened
in C. It is, however, quite an invasive change.

kernelBase_addr -> pptrBase
kernelBase -> pptrBase
physMappingOffset -> ptrBaseOffset

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-11-16 16:52:40 +11:00
Corey Lewis 7baa19495f spec proof: resolve_address_bits'.simps[simp del]
Remove resolve_address_bits'.simps from the simp set at the definition
site, instead of in the middle of the proofs.

Signed-off-by: Corey Lewis <Corey.Lewis@data61.csiro.au>
2020-11-09 17:18:41 +11:00
Gerwin Klein a45adef66a all: remove theory import path references
In Isabelle2020, when isabelle jedit is started without a session
context, e.g. `isabelle jedit -l ASpec`, theory imports with path
references cause the isabelle process to hang.

Since sessions now declare directories, Isabelle can find those files
without path reference and we therefore remove all such path references
from import statements. With this, `jedit` and `build` should work with
and without explicit session context as before.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-11-02 10:16:17 +10:00
Gerwin Klein f45f587536 x64 refine: update to Isabelle2020
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein 300d62e6b3 riscv refine: update to Isabelle2020
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein a8f3f660e4 fixup arm-hyp refine: isa2020
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein f9527fb9ce arm refine: repair EmptyFail_R for Isabelle2020
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein 36d5bfdb1c arm_hyp refine: Isabelle2020 update
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein 6719ec050b arm orphanage: Isabelle2020 update
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein 66b2774155 arm refine: Isabelle2020 update
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein 4c3bbfb059 refine: session directories for Isabelle2020
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Gerwin Klein e7fb36b7e2 ROOT files: file reorg for new ROOT requirements
Isabelle2020 requires each session to declare it own set of directories that
may not overlap with other session's directories. This commit reorganises
files to comply with that requirement.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-10-27 15:52:31 +10:00
Miki Tanaka 0b9c186eb0 armhyp/x64/riscv64 refine: remove interrupt/irq from p_monad
- fix armhyp/x64/riscv64 Refine for the above change

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2020-10-25 13:15:00 +11:00
Miki Tanaka 0359fb1da0 arm refine: remove interrupt/irq from p_monad
- fix ARM refine proofs for the above change
- use dc instead of intr

Signed-off-by: Miki Tanaka <miki.tanaka@data61.csiro.au>
2020-10-25 13:15:00 +11:00
Matthew Brecknell b77f83c57b riscv: rename sbadaddr -> stval
Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2020-08-26 15:24:06 +10:00
Gerwin Klein 4782dc369b
lib/riscv refine: move lemma (#33)
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-08-10 09:14:27 +08:00
Gerwin Klein b356f65969 lib: in_case and find_case methods
We already have find_goal, but the interface is a bit too unwieldy to
casually use frequently. This commit introduces (or moves from RISCV)
two methods on top of find_goal:

 - `in_case x`: asserts the goal has an assumption `?t = x`
 - `find_case x`: finds a goal such that `in_case x`

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-13 11:59:43 +08:00
Gerwin Klein c3f3656942 refine + crefine: proof updates for haskell datatype selectors
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-09 10:06:31 +08:00
Gerwin Klein f0b1c4a044 refine: proof fixes for cong rule tweak
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-08 20:18:31 +08:00
Gerwin Klein 479f98de67 arm_hyp refine: add an Orphanage place holder
This makes sure Isabelle doesn't complain about a missing dependency in
the ROOT file when ARM_HYP is selected. The complaint only shows up in
jedit, and doesn't stop anything, but it's still nicer without.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-02 11:30:56 +08:00
Gerwin Klein 5ee37bd11e refine: replace DomainTime_R by assertion
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-07-02 11:30:56 +08:00
Rafal Kolanski 99d241d031 riscv: clear out most crefine FIXMEs
Perform moves, remove lemmas placed in lib, etc.

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:11 +08:00
Gerwin Klein e7f6e97c6b cleanup: remove stray diagnostic commands and comments
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 81117dc587 riscv cleanup: remove stray diagnostic commands
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein c3ef1c509e arm-hyp refine: fix PageTableDuplicates
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Victor Phan 34e58376a3 arm refine: update for interrupt functions arch split
Signed-off-by: Victor Phan <Victor.Phan@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 9bf346481e x64 refine: proof updates for new arch split functions
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 26a49fcbde arm_hyp refine: proof updates for new arch split functions
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 10457db1b5 riscv orphanage: adapt to new arch split function
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 62e52c84cb riscv refine: adapt to new arch split function
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 0bdec8a194 riscv refine: adjust proofs to new invokeIRQHandler
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 8e60a9af3e riscv refine: prove new lookupPTFromLevel assertion
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:10 +08:00
Gerwin Klein 4ecd369a2d riscv refine: adjust proof for modified assertions
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein 8e4cc14c55 riscv refine: update proof for potential InvalidPTE mappings
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein 14206e2536 riscv refine: prove new Haskell assertions
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein 70ee5750f6 riscv haskell+refine: add assertion to setVMRoot
The assertion is provable from the abstract invariants, and used in
CRefine to conclude that the test wether the vspace root cap is mapped
can be left out.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Gerwin Klein cd82381ae2 riscv refine: add irq ~= irqInvalid to valid_cap'
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Rafal Kolanski e93a475bd6 riscv refine: update for tcbBlockSizeBits == 10
Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-06-08 20:41:09 +08:00
Rafal Kolanski c4f6572aff arm+arm-hyp: move TPIDRURO from vcpu to tcb context
Update specs and proofs for ARM platforms to contain TPIDRURO in the
TCB user context rather than treating it as a VCPU register, following
change in C.

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
2020-05-15 13:14:24 +10:00
Gerwin Klein 71e7f87614 haskell/refine/crefine: rename isBlocked to isStopped
sync with corresponding change in C

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-05-06 15:49:02 +10:00
Gerwin Klein 2574ea6bc0 refine: remove duplicate update rule
makes use of the actual warning in add_upd_simps that was hidden in the
noise before.

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-05-04 17:03:09 +08:00
Victor Phan 190d3b402a riscv spec/ainvs: update IRQs to target hifive platform
- Increase IRQ word size from 3 to 6 to match IRQ_CNODE_SLOT_BITS in
  sel4 config.
- Bump maxIRQ up to 54.
- Fix broken inequality proof by changing constant that depended on IRQ
  word size.
2020-03-27 15:50:46 +11:00
Gerwin Klein c68915b92b license: provide documentation under CC-BY-SA-4.0
Datat61 provides all docs under CC-BY-SA-4.0.
2020-03-16 14:19:15 +08:00
Gerwin Klein a424d55e3e licenses: convert license tags to SPDX 2020-03-13 14:38:24 +08:00
Gerwin Klein 8d12d8e4be licenses: tag .md and document file 2020-03-02 18:52:15 +08:00
Victor Phan 966734c69b Collect abstract lemmas in Refine
Create ArchMove_R.thy for transporting arch specific lemmas (and generic
lemmas that are used somewhat specifically by one architecture) to theory
files before Refine.

Create Move_R.thy as an arch generic Refine theory file for transporting
generic lemmas to theory files before Refine.

Also delete some lemmas that have existed earlier already or are not
needed.

Rename Move.thy in CRefine to Move_C.thy for consistency.
2020-02-21 11:49:25 +11:00
Rafal Kolanski f9ea44ef89 arm-hyp: update spec+proofs for multi-VM support
Highlights:
- new reserved IRQ and associated handler: VPPIEvent
- VPPI events are virtual interrupts we can forward to VMs; currently there is
  only one event: virtual timer interrupt
- VGICMaintenance and VPPIEvent can both receive late interrupts from hardware,
  which are now discarded instead of being delivered to current thread
- given only one possible VPPI event, simplifier tends to mop up more than it
  should, making some proofs fragile w.r.t. adding a new VPPI event
- the order of some lemmas/specs needed shuffling, as now VCPU code needs some
  interrupt code, which uses VCPU code
2020-02-19 10:52:07 +11:00
Zoltan Kocsis 788b4bd180 refactored irq_t structure (VER-1159) 2020-02-05 17:58:45 +11:00
Victor Phan f2d1f5ada7 refine/crefine: convert crunch with multiple constants into crunches 2020-02-03 16:29:19 +11:00
Victor Phan 285c47f622 cleanup for crunch_ignore in refine and crefine for all arches
Several constants are are added to the top level crunch_ignore statement in
Bits_R.thy, then removed from individual crunch statements across Refine and
CRefine.
2020-02-03 16:29:18 +11:00
Gerwin Klein 54f557f2b2 refine: invocation label proof updates 2020-02-03 12:56:19 +08:00
Victor Phan ff6c0d8a0a Move vcpu_switch into Arch_switchToThread and update proofs
Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.
2020-01-20 16:53:32 +11:00
Victor Phan b9c285400d remove diminished (VER-1158)
diminished takes two caps and asserts that one is equal to the other
except that one may have fewer rights. We remove this definition and all
references to it, replacing diminished with equality.
2019-11-16 01:03:36 +11:00
Gerwin Klein c390ba7404 proofs: adjustments for word_lib changes 2019-11-15 12:08:22 +11:00
Gerwin Klein 55aeefdb64 x64: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Gerwin Klein b820b13d06 riscv: avoid automatic unfolding of handle_vm_fault
(fun -> definition)
2019-11-15 12:04:50 +11:00
Victor Phan f8b7f61445 riscv refine: update and close sorries for adding IRQ invocations
irqInvalid is manually requalified into Interrupt_R. If it's defined for all
architectures, then can be requalified instead in the more suitable
spec/machine/MachineExports.thy

Reimplement the following primrecs:
- arch_irq_control_inv_relation
- arch_irq_control_inv_valid'
- irq_control_inv_valid'

Add the following lemmas:
- arch_check_irq_corres
- crunches arch_check_irq, checkIRQ
- arch_check_irq_valid
- arch_check_irq_valid'
- no_fail_setIRQTrigger
- setIRQTrigger_corres
- dmo_setIRQTrigger_invs'
2019-11-12 18:28:40 +11:00
Victor Phan 3ef1e6845c riscv refine: update after adding thread id registers to TCB 2019-11-12 18:28:40 +11:00
Victor Phan e4d83b313a riscv refine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-11-12 18:28:40 +11:00
Gerwin Klein a5e27933a5 riscv: cleanup; resolve remaining FIXMEs 2019-11-12 18:28:40 +11:00
Gerwin Klein d2584a3692 cleanup: collect word lemmas 2019-11-12 18:28:40 +11:00
Gerwin Klein cbc31e31e1 ainvs+refine: provide def of mask_range in InvariantsPre
(used to be ptr_range in riscv, which is too overloaded)
2019-11-12 18:28:40 +11:00
Gerwin Klein 9d81f85c38 riscv: force vptr alignment in PTMap decode
Instead of checking for alignment, mask out the bottom bits to force the
vptr stored in the cap into the correct alignment for the level to be mapped.

See also SELFOUR-2162
2019-11-12 18:28:39 +11:00
Gerwin Klein 12f2d82f86 riscv refine: Orphanage sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein bda92556d7 riscv refine: sorried Orphanage 2019-11-12 18:28:39 +11:00
Gerwin Klein aae4ea5ad0 riscv refine: add EmptyFail_H 2019-11-12 18:28:39 +11:00
Gerwin Klein 72032d8495 riscv refine: cleanup in Finalise_R 2019-11-12 18:28:39 +11:00
Gerwin Klein d06030a524 riscv refine: cleanup in Syscall_R 2019-11-12 18:28:39 +11:00
Gerwin Klein d28bda221f riscv refine: cleanup in ADT_H 2019-11-12 18:28:39 +11:00
Gerwin Klein bc63e2cadb riscv refine: cleanup in Interrupt_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 4f1e8e51ee riscv refine: cleanup in Tcb_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 4bd67d3c4e riscv refine: clean up theory imports + fix fallout 2019-11-12 18:28:39 +11:00
Gerwin Klein 41b4824bf7 riscv refine: cleanup in CSpace1_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 4debd4a44c riscv refine: cleanup in VSpace_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 6cb6814420 riscv refine: cleanup Detype_R 2019-11-12 18:28:39 +11:00
Gerwin Klein eb3f90a815 riscv refine: strengthen word lemmas around mask 2019-11-12 18:28:39 +11:00
Gerwin Klein 66d43a5e91 riscv refine: cleanup in Retype_R 2019-11-12 18:28:39 +11:00
Gerwin Klein eb8370e18e riscv refine: cleanup pass through Invariants_H 2019-11-12 18:28:39 +11:00
Gerwin Klein ec38460345 riscv refine: cleanup pass through ArchAcc_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 7cbe59e67a riscv refine: 0 sorries 2019-11-12 18:28:39 +11:00
Gerwin Klein 04cac93bbe riscv refine: style cleanup in ADT_H
more consistent indentation and definition style;
removed warnings;
removed (most) magic numbers
2019-11-12 18:28:39 +11:00
Gerwin Klein 3d6b5970f7 riscv refine: remove trivial sorry in ADT_H 2019-11-12 18:28:39 +11:00
Gerwin Klein 0ac198fab5 riscv refine: Arch_R sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein f55200b9d9 riscv refine: reduced Arch_R to 1 sorry 2019-11-12 18:28:39 +11:00
Gerwin Klein 41d525d1b6 riscv refine: reduce sorries in Arch_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 53198e4fce riscv refine: VSpace_R sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein b051b9437d riscv refine: reduce sorries in VSpace_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 3f5aaa6c48 riscv refine: Finalise_R sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein be62cf1cfd riscv refine: reduce sorries in VSpace_R and Arch_R 2019-11-12 18:28:39 +11:00
Gerwin Klein ed3d2e1ec2 riscv refine: reduce sorries in VSpace_R 2019-11-12 18:28:39 +11:00
Gerwin Klein e44423d6bb riscv refine: ArchAcc_R sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein a612a0e54e riscv refine: reduce ArchAcc_R sorries to 1 2019-11-12 18:28:39 +11:00
Gerwin Klein 939201f782 riscv refine: Retype_R and Detype_R sorry-free 2019-11-12 18:28:39 +11:00
Gerwin Klein cd70459771 riscv refine: reduce sorries in Finalise_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 5ac27afad0 riscv refine: close all sorries in CNodeInv_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 98a3efe16a riscv refine: close all sorries in Ipc_R 2019-11-12 18:28:39 +11:00
Gerwin Klein fe895506cc riscv refine: 0 sorries in Syscall_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 1f539c062c riscv refine: 0 sorries in Refine_R 2019-11-12 18:28:39 +11:00
Gerwin Klein bf83335d78 riscv refine: reduce sorries in Refine 2019-11-12 18:28:39 +11:00
Gerwin Klein 2d9ec1736f riscv refine: set up DomainTime_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein d224325b43 riscv refine: add Orphanage (dummy file)
This file is needed to prevent error messages in ROOT. No-orphans proof is
currently still ARM-only.
2019-11-12 18:28:39 +11:00
Gerwin Klein bd8e032504 riscv refine: sorrying Refine_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 6b2009ac45 riscv refine: set up IncKernelInit, InitLemmas, KernelInit_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein cbe29f527f riscv refine: sorrying ADT_H (3 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 4a5084b46b riscv refine: encode absence of Execute in PTablePTEs in state relation 2019-11-12 18:28:39 +11:00
Gerwin Klein b692a5c81f riscv refine: set up PageTableDuplicates (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein eab8f3e19e riscv refine: set up Syscall_R (3 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 1d9328dbcd riscv refine: set up Tcb_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein d324216454 riscv refine: set up CNodeInv (3 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 0d881171fa riscv refine: set up Interrupt_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 42bd55ea3b riscv refine: simplify assumptions in CSpace_R 2019-11-12 18:28:39 +11:00
Gerwin Klein b1157aef9e riscv refine: sorrying Ipc_R (2 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein bdf9e036a8 riscv refine: sorrying Arch_R (7 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 99b7cc7ceb riscv refine: remove unused assumptions 2019-11-12 18:28:39 +11:00
Gerwin Klein 5ee57f72fc riscv refine: sorrying Finalise_R (3 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 45172e930f riscv refine: basic setup for recursive PTLookup* 2019-11-12 18:28:39 +11:00
Gerwin Klein 76a69cda63 riscv refine: close sorry in KHeap_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 96b3754455 riscv refine: set up IpcCancel (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein e6da934e7d riscv refine: simplify setASIDPool_invs
Does not require valid_asid_pool in weakened invariant setting.
2019-11-12 18:28:39 +11:00
Gerwin Klein e46023fe12 riscv refine: set up Untyped_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 159bf6a50f riscv refine: add valid_arch_cap' to invariants
It turns out that Untyped_R needs the properties of valid_arch_cap' non-locally
for all descendants of the untyped cap it's looking at. This would be a fairly
involved property to assert, and so far only Retype/Detype had any real proof
obligations on valid_cap', i.e. it should be cheap to keep.
2019-11-12 18:28:39 +11:00
Gerwin Klein 854e74a1fd riscv refine: add Invocations_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 4422d1ecca riscv refine: sorried Detype_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 2d9afdf7be riscv refine: storePTE_valid_objs + remove one sorry 2019-11-12 18:28:39 +11:00
Gerwin Klein adf7f7bf03 riscv refine: sorry Retype_R (2 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 01c6c9f7b5 riscv refine: weaken precondition of threadSet_invs_trivialT 2019-11-12 18:28:39 +11:00
Gerwin Klein 4fe875e854 riscv refine: set up Schedule_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein e850ab5ea5 riscv refine: reduce Haskell guards in TcbAcc 2019-11-12 18:28:39 +11:00
Gerwin Klein c40435c4a8 riscv refine: sorried VSpace_R 2019-11-12 18:28:39 +11:00
Gerwin Klein e25631e919 riscv refine: more guard cross-over rules 2019-11-12 18:28:39 +11:00
Gerwin Klein d4932ced42 riscv refine: set up InterruptAcc_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 7fde8b47a0 riscv refine: set up TcbAcc_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein df28d3bdbc riscv refine: set up CSpace_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 3d037d7219 riscv refine: Invariants_H: syntax precedence for parentOf 2019-11-12 18:28:39 +11:00
Gerwin Klein b122d1945a riscv refine: fill in RAB_FN.thy 2019-11-12 18:28:39 +11:00
Gerwin Klein a3dd552343 riscv refine: set up CSpace1_R (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 6cd1482169 riscv refine: set up CSpace_I (0 sorries) 2019-11-12 18:28:39 +11:00
Gerwin Klein 1f149e7387 riscv refine: add ArchFrameCap to capSimps and friends 2019-11-12 18:28:39 +11:00
Gerwin Klein 7815e4734a riscv refine: introduce bit_simps' 2019-11-12 18:28:39 +11:00
Gerwin Klein e6fe4420ea riscv refine: sorried ArchAcc_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 318d54a8ca riscv refine: adjustments for page_table_at' in KHeap_R 2019-11-12 18:28:39 +11:00
Gerwin Klein 8b40b334bd riscv refine: rephrase page_table_at' in Invariants_H 2019-11-12 18:28:38 +11:00
Gerwin Klein c4646172b3 riscv refine: set up KHeap_R (1 sorry) and SubMonad_R 2019-11-12 18:28:38 +11:00
Gerwin Klein 6bc51a2562 riscv refine: set up Bits_R, Corres, EmptyFail 2019-11-12 18:28:38 +11:00
Gerwin Klein db8768234c riscv refine: initial state relation 2019-11-12 18:28:38 +11:00
Gerwin Klein 244e8fe32f riscv refine: initial design invariants
upd
2019-11-12 18:28:38 +11:00
Gerwin Klein 8be2ab8484 riscv refine: initial skeleton 2019-11-12 18:28:38 +11:00
Corey Lewis 9846cd42bb proof: update for crunch changes 2019-10-14 17:23:41 +11:00
Corey Lewis dd48e0d899 proof: update for wp changes
Updated 'wp_once' to 'wp (once)' and removed several stray uses of 'wp_trace'.
2019-10-14 17:12:18 +11:00
Victor Phan a6024fb377 x64 refine/crefine: remove vmsz_aligned' 2019-10-10 11:27:31 +11:00
Victor Phan 9100315c86 x64 refine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-10-10 11:27:10 +11:00
Victor Phan c5b4d0fab5 arm-hyp refine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-10-10 11:27:10 +11:00
Victor Phan 67d37f8025 arm refine: update for PageMap replacing PageRemap (SELFOUR-161) 2019-10-10 11:27:10 +11:00
MiladKetabi acbc08b836 clean-ups done during proof update for the jira issue SELFOUR-1187: seL4 setPriority should attempt a direct schedule 2019-10-06 18:31:19 +11:00
MiladKetabi d934d25269 proof update for SELFOUR-1187: seL4 setPriority should attempt a direct schedule
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.
2019-10-06 18:31:19 +11:00
Gerwin Klein ab4b3b17c6 refine: adjustments for global None_upd_eq[simp] 2019-07-31 16:55:32 +10:00
Amirreza Zarrabi 4f93ebe608 refine, crefine: update after adding thread id registers to TCB for SELFOUR-1524 2019-06-28 11:48:24 +10:00
Gerwin Klein c34840d09b global: isabelle update_cartouches 2019-06-14 11:41:21 +10:00
Michael McInerney 0025f29417 refine: update for Isabelle2019 2019-06-13 16:22:33 +10:00
Michael McInerney 4463e9750e SELFOUR-1198: update proofs for correct restart PC
Fixes a case where a thread can go from Running->Inactive->Restart and
use a restart PC that is out of date. An out of date restart PC occurs
when a thread was transitioned to running after being in a blocked
state, but was never scheduled and so did not execute the traps code
that updates the restart PC.

This also renames relevant register names for consistency across
architectures (FaultIP and NextIP).
2019-06-13 11:43:50 +10:00
Michael McInerney 4a07af9d9d ainvs refine: update arch-split locale names
Previously, some arch-specific names were qualified with the wrong
architecture abbreviation.
2019-06-13 11:43:50 +10:00
Michael McInerney 9478d5507c refine cleanup: remove unused lemmas 2019-06-13 11:43:50 +10:00
Michael McInerney 6d581b5897 refine: add some lemmas about obj_at' 2019-06-13 11:43:50 +10:00
Edward Pierzchalski c1e9a09e26 lib: move "tl_nat_list_simp" up. 2019-05-28 10:00:10 +10:00
Edward Pierzchalski 14c4722cef refine: remove stray 'thm' commands. 2019-05-28 10:00:10 +10:00
Edward Pierzchalski 59b07ad60d refine: mark "call_kernel_serial" as a theorem. 2019-05-28 10:00:10 +10:00
Edward Pierzchalski 2035f444a0 refine: Remove unused lemmas. 2019-05-28 10:00:10 +10:00
Matthew Brecknell f1901beee0 cleanup: remove duplicates of invs'_invs_no_cicd 2019-05-03 13:52:52 +10:00
Matthew Brecknell eedf3d8fa2 cleanup: remove duplicates of objBitsKO_gt_0 2019-05-03 13:52:52 +10:00
Victor Phan 834dd88681 refine: remove as_user_valid_etcbs from architecture specific files
as_user_valid_etcbs can be reasoned in an architecture generic setting.
2019-04-18 14:32:08 +10:00
Victor Phan 1689dd94fe cleanup
arm ainvs: cleanup

Abbreviate Hoare triples that do not care about the return value and
whose pre and post conditions are the same.

x64 ainvs: cleanup

ainvs: cleanup

x64 ainvs: cleanup

drefine: cleanup
2019-04-18 14:32:08 +10:00
Victor Phan 1fd4c1ab0b x64 refine: update for new definition of set_object 2019-04-18 14:32:08 +10:00
Victor Phan c323da2f5c arm-hyp refine: update for new definition of set_object 2019-04-18 14:32:08 +10:00
Victor Phan d707c97df9 arm refine: update for new definition of set_object 2019-04-18 14:32:08 +10:00
Rafal Kolanski 103fc3656e x64 refine: update for GrantReply (SELFOUR-6) 2018-12-10 20:01:38 +11:00